Loading arch/arm/boot/dts/qcom/msm8916.dtsi +5 −1 Original line number Diff line number Diff line Loading @@ -1207,6 +1207,8 @@ i2c_0: i2c@78b6000 { /* BLSP1 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78b6000 0x600>, <0x7884000 0x23000>; Loading @@ -1229,6 +1231,8 @@ i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78b9000 0x600>, <0x7884000 0x23000>; Loading @@ -1252,7 +1256,7 @@ i2c_6: i2c@78ba000 { /* BLSP1 QUP6 */ compatible = "qcom,i2c-msm-v2"; #address-cells=<1>; #sice-cells=<0>; #size-cells=<0>; cell-index = <6>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78ba000 0x1000>, Loading Loading
arch/arm/boot/dts/qcom/msm8916.dtsi +5 −1 Original line number Diff line number Diff line Loading @@ -1207,6 +1207,8 @@ i2c_0: i2c@78b6000 { /* BLSP1 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78b6000 0x600>, <0x7884000 0x23000>; Loading @@ -1229,6 +1231,8 @@ i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78b9000 0x600>, <0x7884000 0x23000>; Loading @@ -1252,7 +1256,7 @@ i2c_6: i2c@78ba000 { /* BLSP1 QUP6 */ compatible = "qcom,i2c-msm-v2"; #address-cells=<1>; #sice-cells=<0>; #size-cells=<0>; cell-index = <6>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78ba000 0x1000>, Loading