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Commit d12e388e authored by Sarangdhar Joshi's avatar Sarangdhar Joshi
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ARM: dts: msm: add nidnt dt entry for msmzirc 



Add CoreSight device tree entry for NIDnT mode required to support Serial
Wire Debug, UART and Trace modes through SD card interface.

Change-Id: I3ee4aadc9d14956657f57e0184d1d1a3e79dec3f
Signed-off-by: default avatarSarangdhar Joshi <spjoshi@codeaurora.org>
parent c0fa49de

arch/arm/boot/dts/qcom/msmzirc-coresight.dtsi

+19 −4
Original line number Diff line number Diff line
@@ -33,13 +33,27 @@ 


	tpiu: tpiu@820000 {

		compatible = "arm,coresight-tpiu";

		reg = <0x820000 0x1000>;

		reg-names = "tpiu-base";

		reg = <0x820000 0x1000>,

		      <0x1100000 0xb0000>;

		reg-names = "tpiu-base", "nidnt-base";



		coresight-id = <1>;

		coresight-name = "coresight-tpiu";

		coresight-nr-inports = <1>;



		qcom,nidntsw;

		qcom,nidnthw;

		qcom,nidnt-swduart;

		qcom,nidnt-swdtrc;

		qcom,nidnt-jtag;

		qcom,nidnt-spmi;



		nidnt-gpio = <38>;

		nidnt-gpio-polarity = <1>;



		interrupts = <0 82 0>;

		interrupt-names = "nidnt-irq";



		vdd-supply = <&pmd9635_l11>;

		qcom,vdd-voltage-level = <2950000 2950000>;

		qcom,vdd-current-level = <15000 400000>;
@@ -349,8 +363,9 @@ 


	fuse: fuse@5e01c {

		compatible = "arm,coresight-fuse-v2";

		reg = <0x5e01c 0x8>;

		reg-names = "fuse-base";

		reg = <0x5e01c 0x8>,

		      <0x58040 0x4>;

		reg-names = "fuse-base", "nidnt-fuse-base";



		coresight-id = <22>;

		coresight-name = "coresight-fuse-v2";