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Commit d0cbdfdd authored by Taniya Das's avatar Taniya Das Committed by Stephen Boyd
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ARM: gic: save/restore distributor ISR register values 



Before going into power collapse we have to save/restore the ISR
registers in case we configure GIC to handle FIQ on apps side.
Otherwise we will end up in wrong ISR configurations after PC.

Change-Id: Ib58b701fc462c10ec88576feab3c8a9eb3027009
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent a673bfcd

drivers/irqchip/irq-gic.c

+12 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ struct gic_chip_data { 
	u32 __percpu *saved_ppi_enable;

	u32 __percpu *saved_ppi_conf;

#endif

	u32 saved_dist_isr[DIV_ROUND_UP(1020, 32)];

	struct irq_domain *domain;

	unsigned int gic_irqs;

#ifdef CONFIG_GIC_NON_BANKED
@@ -679,6 +680,11 @@ static void gic_dist_save(unsigned int gic_nr) 
	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)

		gic_data[gic_nr].saved_spi_enable[i] =

			readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);

	if (is_cpu_secure()) {

		for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)

			gic_data[gic_nr].saved_dist_isr[i] =

				readl_relaxed(dist_base + GIC_DIST_IGROUP + i * 4);

	}

}



/*
@@ -721,6 +727,12 @@ static void gic_dist_restore(unsigned int gic_nr) 
		writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],

			dist_base + GIC_DIST_ENABLE_SET + i * 4);



	if (is_cpu_secure()) {

		for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)

			writel_relaxed(gic_data[gic_nr].saved_dist_isr[i],

					dist_base + GIC_DIST_IGROUP + i * 4);

	}



	writel_relaxed(saved_dist_ctrl, dist_base + GIC_DIST_CTRL);

}