Merge "clk: qcom: mdss: Add mdss pll clock driver support"

Qualcomm MDSS pll for DSI/EDP/HDMI

mdss-pll is a pll controller device which supports pll devices that

are compatable with MIPI display serial interface specification,

HDMI and edp.

Required properties:

- compatible:		Compatible name used in the driver

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

- gdsc-supply:		Phandle for gdsc regulator device node.

- vddio-supply:		Phandle for vddio regulator device node.

- clock-names:		List of clock names needed by the device.

- clock-rate:		List of clock rates in Hz.

Optional properties:

- label:	       	A string used to describe the driver used.

- qcom,platform-supply-entries:	A node that lists the elements of the supply. There

				can be more than one instance of this binding,

				in which case the entry would be appended with

				the supply entry index.

				e.g. qcom,platform-supply-entry@0

				- reg: offset and length of the register set for the device.

				-- qcom,supply-name: name of the supply (vdd/vdda/vddio)

				-- qcom,supply-min-voltage: minimum voltage level (uV)

				-- qcom,supply-max-voltage: maximum voltage level (uV)

				-- qcom,supply-enable-load: load drawn (uA) from enabled supply

				-- qcom,supply-disable-load: load drawn (uA) from disabled supply

				-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on

				-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on

				-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off

				-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off

Example:

	mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 {

		compatible = "qcom,mdss_dsi_pll";

		label = "MDSS DSI 0 PLL";

		cell-index = <0>;

		reg = <0xfd922A00 0xD4>;

		reg-names = "pll_base";

		gdsc-supply = <&gdsc_mdss>;

		vddio-supply = <&pm8941_l12>;

		clock-names = "mdp_core_clk", "iface_clk", "bus_clk";

		clock-rate = <0>, <0>, <0>;

		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vddio";

				qcom,supply-min-voltage = <1800000>;

				qcom,supply-max-voltage = <1800000>;

				qcom,supply-enable-load = <100000>;

				qcom,supply-disable-load = <100>;

				qcom,supply-pre-on-sleep = <0>;

				qcom,supply-post-on-sleep = <20>;

				qcom,supply-pre-off-sleep = <0>;

				qcom,supply-post-off-sleep = <0>;

			};

		};

	};

config MSM_MDSS_PLL

	bool "MDSS pll programming"

	---help---

	It provides support for DSI, eDP and HDMI interface pll programming on MDSS

	hardware. It also handles the pll specific resources and turn them on/off when

	mdss pll client tries to enable/disable pll clocks.

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll-util.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28hpm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o

/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#ifndef __MDSS_DSI_PLL_H

#define __MDSS_DSI_PLL_H

#define MAX_DSI_PLL_EN_SEQS	10

struct lpfr_cfg {

	unsigned long vco_rate;

	u32 r;

};

struct dsi_pll_vco_clk {

	unsigned long	ref_clk_rate;

	unsigned long	min_rate;

	unsigned long	max_rate;

	u32		pll_en_seq_cnt;

	struct lpfr_cfg *lpfr_lut;

	u32		lpfr_lut_size;

	void		*priv;

	struct clk	c;

	int (*pll_enable_seqs[MAX_DSI_PLL_EN_SEQS])

			(struct mdss_pll_resources *dsi_pll_Res);

};

int dsi_pll_clock_register(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res);

#endif