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Commit cfdcfc46 authored by Jeykumar Sankaran's avatar Jeykumar Sankaran
Browse files

msm: mdss: Use target specific ping pong buffer register offsets 



Use target specific ping pong buffer register offsets instead
of hard coded ones to program control and config parameters.

Change-Id: Id446452d6ff42e886b8e3232a1143c1b0a742489
Signed-off-by: default avatarJeykumar Sankaran <jsanka@codeaurora.org>
parent f7d25bdf

Documentation/devicetree/bindings/fb/mdss-mdp.txt

+5 −0
Original line number Diff line number Diff line
@@ -368,6 +368,10 @@ Optional properties: 
				    clients.

- qcom,mdss-dram-channels:	This represents the number of channels in the

				Bus memory controller.

- qcom,mdss-ppb-off:		Array of offset addresses of ping pong buffer control registers.

				The offsets are calculated from the "mdp_phys" base address

				specified. The number of offsets should match the

				number of ping pong buffers available in the hardware.



Fudge Factors:			Fudge factors are used to boost demand for

				resources like bus bandswidth, clk rate etc. to
@@ -595,6 +599,7 @@ Example: 
				    0x00017100 0x00019100>;

		qcom,mdss-intf-off = <0x00021100 0x00021300

					   0x00021500 0x00021700>;

		qcom,mdss-ppb-off = <0x0000420>;



		/* buffer parameters to calculate prefill bandwidth */

		qcom,mdss-prefill-outstanding-buffer-bytes = <1024>;

drivers/video/msm/mdss/mdss.h

+7 −0
Original line number Diff line number Diff line
@@ -99,6 +99,11 @@ struct mdss_prefill_data { 
	u32 fbc_lines;

};



struct mdss_mdp_ppb {

	u32 ctl_off;

	u32 cfg_off;

};



enum mdss_hw_index {

	MDSS_HW_MDP,

	MDSS_HW_DSI0 = 1,
@@ -224,6 +229,8 @@ struct mdss_data_type { 
	u32 max_target_zorder;

	u8  ncursor_pipes;

	u32 max_cursor_size;

	u32 nppb;

	struct mdss_mdp_ppb *ppb;



	struct mdss_mdp_mixer *mixer_intf;

	struct mdss_mdp_mixer *mixer_wb;

drivers/video/msm/mdss/mdss_mdp.c

+30 −1
Original line number Diff line number Diff line
@@ -169,7 +169,7 @@ static int mdss_mdp_parse_dt_prefill(struct platform_device *pdev); 
static int mdss_mdp_parse_dt_misc(struct platform_device *pdev);

static int mdss_mdp_parse_dt_ad_cfg(struct platform_device *pdev);

static int mdss_mdp_parse_dt_bus_scale(struct platform_device *pdev);



static int mdss_mdp_parse_dt_ppb_off(struct platform_device *pdev);

/**

 * mdss_mdp_vbif_axi_halt() - Halt MDSS AXI ports

 * @mdata: pointer to the global mdss data structure.
@@ -1756,6 +1756,10 @@ static int mdss_mdp_parse_dt(struct platform_device *pdev) 
		return rc;

	}



	rc = mdss_mdp_parse_dt_ppb_off(pdev);

	if (rc)

		pr_debug("Info in device tree: ppb offset not configured\n");



	/* Parse the mdp specific register base offset*/

	rc = of_property_read_u32(pdev->dev.of_node,

		"qcom,mdss-mdp-reg-offset", &data);
@@ -2790,6 +2794,31 @@ parse_done: 
	return rc;

}



static int mdss_mdp_parse_dt_ppb_off(struct platform_device *pdev)

{

	struct mdss_data_type *mdata = platform_get_drvdata(pdev);

	u32 len, index;

	const u32 *arr;

	arr = of_get_property(pdev->dev.of_node, "qcom,mdss-ppb-off", &len);

	if (arr) {

		mdata->nppb = len / sizeof(u32);

		mdata->ppb = devm_kzalloc(&mdata->pdev->dev,

				sizeof(struct mdss_mdp_ppb) *

				mdata->nppb, GFP_KERNEL);



		if (mdata->ppb == NULL)

			return -ENOMEM;



		for (index = 0; index <  mdata->nppb; index++) {

			mdata->ppb[index].ctl_off = be32_to_cpu(arr[index]);

			mdata->ppb[index].cfg_off =

				mdata->ppb[index].ctl_off + 4;

		}

		return 0;

	}

	return -EINVAL;

}



static int mdss_mdp_parse_dt_bus_scale(struct platform_device *pdev)

{

	int rc;

drivers/video/msm/mdss/mdss_mdp_ctl.c

+12 −5
Original line number Diff line number Diff line
@@ -2284,16 +2284,23 @@ static void mdss_mdp_ctl_dst_split_display_enable(int enable, 
{

	u32 config = 0, cntl = 0;



	if (ctl->mdata->nppb == 0) {

		pr_err("No PPB to enable PP split\n");

		BUG();

	}



	mdss_mdp_ctl_split_display_enable(enable, ctl, NULL);



	if (enable) {

		config = BIT(16); /* Set horizontal split*/

		/* Set slave intf */

		config = ((ctl->intf_num + 1) - MDSS_MDP_INTF0) << 20;

		config |= BIT(16); /* Set horizontal split*/

		cntl = BIT(5); /* enable dst split*/

	}



	writel_relaxed(config, ctl->mdata->mdp_base +

		MDSS_MDP_REG_PPB0_CONFIG);

	writel_relaxed(cntl, ctl->mdata->mdp_base +

		MDSS_MDP_REG_PPB0_CNTL);

			ctl->mdata->ppb[0].cfg_off);

	writel_relaxed(cntl, ctl->mdata->mdp_base + ctl->mdata->ppb[0].ctl_off);

}



int mdss_mdp_ctl_destroy(struct mdss_mdp_ctl *ctl)

drivers/video/msm/mdss/mdss_mdp_hwio.h

+0 −3
Original line number Diff line number Diff line
@@ -53,9 +53,6 @@ 
#define MDSS_MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTRL	0x002F8

#define MDSS_MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTRL	0x003F0



#define MDSS_MDP_REG_PPB0_CNTL		0x00420

#define MDSS_MDP_REG_PPB0_CONFIG	0x00424



#define MDSS_INTF_DSI	0x1

#define MDSS_INTF_HDMI	0x3

#define MDSS_INTF_LCDC	0x5