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Commit cf5eb976 authored by Zhen Kong's avatar Zhen Kong
Browse files

ARM: dts: msm: Update crypto BW request for FDE on msm8994 



By default qcrypto driver is requesting for higher BW which falls
in turbo mode, so power numbers are higher. This patch request the
BW with the values which fall onto nominal mode on msm8994.

Change-Id: I018ced4aeb56a05bd951d6df297bda135e41285a
Signed-off-by: default avatarZhen Kong <zkong@codeaurora.org>
parent 512860c2

arch/arm/boot/dts/qcom/msm8994.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -2839,7 +2839,7 @@ 
		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

				<55 512 393600 393600>;

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcrypto_ce2_clk>,

			 <&clock_rpm clk_gcc_ce2_ahb_m_clk>,
@@ -2866,7 +2866,7 @@ 
		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

				<55 512 393600 393600>;

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcrypto_ce3_clk>,

			 <&clock_rpm clk_gcc_ce3_ahb_m_clk>,
@@ -2893,7 +2893,7 @@ 
		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

				<55 512 393600 393600>;

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcrypto_ce2_clk>,

			 <&clock_rpm clk_gcc_ce2_ahb_m_clk>,
@@ -2920,7 +2920,7 @@ 
		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

				<55 512 393600 393600>;

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcrypto_ce3_clk>,

			 <&clock_rpm clk_gcc_ce3_ahb_m_clk>,
@@ -2947,7 +2947,7 @@ 
		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

				<55 512 393600 393600>;

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcedev_ce2_clk>,

			 <&clock_rpm clk_gcc_ce2_ahb_m_clk>,