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Commit cf02af54 authored by Saravana Kannan's avatar Saravana Kannan
Browse files

ARM: dts: msm: Add L2 perf monitor interrupts to bypass list 



The L2 perf monitor interrupts can only come when the CPU subsystem is
active and powered on. So, put it in the bypass list so that XO shutdown is
not blocked to allow processing this interrupt when the CPU subsystem is
power collapsed.

Change-Id: I1ae4dc9e800ac2d7188d45ef7634530d93049340
Signed-off-by: default avatarSaravana Kannan <skannan@codeaurora.org>
parent 6d52439a

arch/arm/boot/dts/qcom/msm8974-v2-pm.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -210,6 +210,7 @@ 
			<50 172>, /* usb1_hs_async_wakeup_irq */

			<53 104>, /* mdss_irq */

			<62 222>, /* ee0_krait_hlos_spmi_periph_irq */

			<0xff 33>,  /* APCC_qgicL2PerfMonIrptReq */

			<0xff 34>,  /* APCC_qgicL2ErrorIrptReq */

			<0xff 35>,  /* WDT_barkInt */

			<0xff 40>,  /* qtimer_phy_irq */

arch/arm/boot/dts/qcom/msm8974pro-pm.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -200,6 +200,7 @@ 
			<50 172>, /* usb1_hs_async_wakeup_irq */

			<53 104>, /* mdss_irq */

			<62 222>, /* ee0_krait_hlos_spmi_periph_irq */

			<0xff 33>,  /* APCC_qgicL2PerfMonIrptReq */

			<0xff 34>,  /* APCC_qgicL2ErrorIrptReq */

			<0xff 35>,  /* WDT_barkInt */

			<0xff 40>,  /* qtimer_phy_irq */