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Commit cedf74db authored by Rohit Vaswani's avatar Rohit Vaswani
Browse files

soc: cpu_pwr_ctl: modify the CPU and L2 sequence for 8994-V2 



The CPU and L2 bootup sequence has different timing restrictions for
8994 V2. Modify the sequence as per the recommendations. This should
continue to work for 8994 V1.

Change-Id: Ia31e26f9e616713dc0671792407173e92c5ab44a
Signed-off-by: default avatarRohit Vaswani <rvaswani@codeaurora.org>
parent a3931eb3

drivers/soc/qcom/cpu_pwr_ctl.c

+4 −2
Original line number Diff line number Diff line
@@ -215,7 +215,7 @@ static int power_on_l2_msm8994(struct device_node *l2ccc_node, u32 pon_mask, 
	/* Close L2/SCU Logic GDHS and power up the cache */

	writel_relaxed(0x00029716 , l2_base + L2_PWR_CTL);

	mb();

	udelay(2);

	udelay(8);



	/* De-assert L2/SCU memory Clamp */

	writel_relaxed(0x00023716 , l2_base + L2_PWR_CTL);
@@ -224,6 +224,7 @@ static int power_on_l2_msm8994(struct device_node *l2ccc_node, u32 pon_mask, 
	/* Wakeup L2/SCU RAMs by deasserting sleep signals */

	writel_relaxed(0x0002371E , l2_base + L2_PWR_CTL);

	mb();

	udelay(8);



	/* Un-gate clock and wait for sequential waking up

	 * of L2 rams with a delay of 2*X0 cycles
@@ -352,11 +353,12 @@ int msm8994_unclamp_secondary_arm_cpu(unsigned int cpu) 
	/* De-assert coremem clamp. This is asserted by default */

	writel_relaxed(0x00000079, acc_reg + CPU_PWR_CTL);

	mb();

	udelay(2);



	/* Close coremem array gdhs */

	writel_relaxed(0x0000007D, acc_reg + CPU_PWR_CTL);

	mb();

	udelay(1);

	udelay(2);



	/* De-assert clamp */

	writel_relaxed(0x0000003D, acc_reg + CPU_PWR_CTL);