Merge "EHCI: HSIC: Don't fail probe if clk_get fails for optional clocks" (cc38f099) · Commits · e / devices / android_kernel_sony_msm8994

drivers/usb/host/ehci-msm-hsic.c

+19 −34

Original line number	Diff line number	Diff line
		@@ -1523,7 +1523,7 @@ static int msm_hsic_init_clocks(struct msm_hsic_hcd *mehci, u32 init)

		/*core_clk is required for LINK protocol engine
		clock rate appropriately set by target specific clock driver /
		mehci->core_clk = clk_get(mehci->dev, "core_clk");
		mehci->core_clk = devm_clk_get(mehci->dev, "core_clk");
		if (IS_ERR(mehci->core_clk)) {
		ret = PTR_ERR(mehci->core_clk);
		mehci->core_clk = NULL;
		@@ -1532,48 +1532,35 @@ static int msm_hsic_init_clocks(struct msm_hsic_hcd *mehci, u32 init)
		return ret;
		}

		/* alt_core_clk is for LINK to be used during PHY RESET in
		* targets on which link does NOT use asynchronous reset methodology.
		* clock rate appropriately set by target specific clock driver */
		mehci->alt_core_clk = clk_get(mehci->dev, "alt_core_clk");
		if (IS_ERR(mehci->alt_core_clk)) {
		ret = PTR_ERR(mehci->alt_core_clk);
		mehci->alt_core_clk = NULL;
		if (ret != -EPROBE_DEFER)
		dev_dbg(mehci->dev, "failed to get alt_core_clk\n");
		else
		goto put_core_clk;
		}

		/* phy_clk is required for HSIC PHY operation
		* clock rate appropriately set by target specific clock driver */
		mehci->phy_clk = clk_get(mehci->dev, "phy_clk");
		mehci->phy_clk = devm_clk_get(mehci->dev, "phy_clk");
		if (IS_ERR(mehci->phy_clk)) {
		ret = PTR_ERR(mehci->phy_clk);
		mehci->phy_clk = NULL;
		if (ret != -EPROBE_DEFER)
		dev_err(mehci->dev, "failed to get phy_clk\n");
		goto put_alt_core_clk;
		return ret;
		}

		/* 10MHz cal_clk is required for calibration of I/O pads */
		mehci->cal_clk = clk_get(mehci->dev, "cal_clk");
		mehci->cal_clk = devm_clk_get(mehci->dev, "cal_clk");
		if (IS_ERR(mehci->cal_clk)) {
		ret = PTR_ERR(mehci->cal_clk);
		mehci->cal_clk = NULL;
		if (ret != -EPROBE_DEFER)
		dev_err(mehci->dev, "failed to get cal_clk\n");
		goto put_phy_clk;
		return ret;
		}

		/* ahb_clk is required for data transfers */
		mehci->ahb_clk = clk_get(mehci->dev, "iface_clk");
		mehci->ahb_clk = devm_clk_get(mehci->dev, "iface_clk");
		if (IS_ERR(mehci->ahb_clk)) {
		ret = PTR_ERR(mehci->ahb_clk);
		mehci->ahb_clk = NULL;
		if (ret != -EPROBE_DEFER)
		dev_err(mehci->dev, "failed to get iface_clk\n");
		goto put_cal_clk;
		return ret;
		}

		/*
		@@ -1581,10 +1568,19 @@ static int msm_hsic_init_clocks(struct msm_hsic_hcd *mehci, u32 init)
		* This clock is not compulsory and is defined in clock lookup
		* only for targets that need to use the inactivity timer feature.
		*/
		mehci->inactivity_clk = clk_get(mehci->dev, "inactivity_clk");
		mehci->inactivity_clk = devm_clk_get(mehci->dev, "inactivity_clk");
		if (IS_ERR(mehci->inactivity_clk))
		dev_dbg(mehci->dev, "failed to get inactivity_clk\n");

		/*
		* alt_core_clk is for LINK to be used during PHY RESET in
		* targets on which link does NOT use asynchronous reset methodology.
		* clock rate appropriately set by target specific clock driver
		*/
		mehci->alt_core_clk = devm_clk_get(mehci->dev, "alt_core_clk");
		if (IS_ERR(mehci->alt_core_clk))
		dev_dbg(mehci->dev, "failed to get alt_core_clk\n");

		clk_prepare_enable(mehci->core_clk);
		clk_prepare_enable(mehci->phy_clk);
		clk_prepare_enable(mehci->cal_clk);
		@@ -1603,21 +1599,10 @@ put_clocks:
		if (!IS_ERR(mehci->inactivity_clk))
		clk_disable_unprepare(mehci->inactivity_clk);
		}
		if (!IS_ERR(mehci->inactivity_clk))
		clk_put(mehci->inactivity_clk);
		clk_put(mehci->ahb_clk);
		put_cal_clk:
		clk_put(mehci->cal_clk);
		put_phy_clk:
		clk_put(mehci->phy_clk);
		put_alt_core_clk:
		if (mehci->alt_core_clk)
		clk_put(mehci->alt_core_clk);
		put_core_clk:
		clk_put(mehci->core_clk);

		return ret;
		return 0;
		}

		static irqreturn_t hsic_peripheral_status_change(int irq, void *dev_id)
		{
		struct msm_hsic_hcd *mehci = dev_id;