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Commit cc36432a authored by Sujit Reddy Thumma's avatar Sujit Reddy Thumma
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ARM: dts: msm: Add DT entries for SATA controller and PHY on APQ8084 



Add AHCI SATA controller and MSM SATA PHY nodes for APQ8084.
APQ8084 supports UFS-SATA combo PHY which means PHY is shared between
SATA and UFS and is mutually exclusive. Hence, add the necessary
DT entries and by default the status of device node is disabled.
SATA should be enabled only on those boards that reworked for the
external differential pins to connect to SATA HDD.

Change-Id: Ib8832edcb15fd57d46aaf229ed50d89282ed9969
Signed-off-by: default avatarVenkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: default avatarSujit Reddy Thumma <sthumma@codeaurora.org>
parent 4456e142

arch/arm/boot/dts/qti/apq8084.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -2253,6 +2253,33 @@ 
		status = "disabled";

	};



	sataphy0: sataphy@0xfc581000 {

		compatible = "qcom,sataphy";

		reg = <0xfc581000 0x400>, <0xfd4ab20c 0x4>;

		reg-names = "phy_mem", "phy_sel";

		#phy-cells = <0>;

		vdda-phy-supply = <&pma8084_l4>;

		vdda-pll-supply = <&pma8084_l12>;

		vdda-phy-max-microamp = <50000>;

		vdda-pll-max-microamp = <1000>;



		status = "disabled";

	};



	sata0: sata@0xfc580000 {

		compatible = "qcom,msm-ahci";

		reg = <0xfc580000 0x400>;

		interrupts = <0 31 0>;



		phys = <&sataphy0>;

		phy-names = "sata-6g";

		clock-names = "core_clk", "iface_clk", "pmalive_clk",

				"rxoob_clk", "asic0_clk", "rbc0_clk";

		max-clock-frequency-hz = <0 0 100000000

					100000000 300000000 300000000>;

		status = "disabled";

	};



	qcom,wdt@f9017000 {

		compatible = "qcom,msm-watchdog";

		reg = <0xf9017000 0x1000>;