Loading arch/arm/boot/dts/qcom/msm8994.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -1403,9 +1403,10 @@ <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_gcc_usb3_phy_reset>, <&clock_gcc clk_gcc_usb3phy_phy_reset>, <&clock_gcc clk_usb_ss_phy_ldo>; clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset", "ldo_clk"; "phy_phy_reset", "ldo_clk"; }; dbm_1p5: dbm@f92f8000 { Loading drivers/clk/qcom/clock-gcc-8994.c +16 −5 Original line number Diff line number Diff line Loading @@ -2484,18 +2484,28 @@ static struct branch_clk gcc_usb3_phy_aux_clk = { }, }; static struct branch_clk gcc_usb3_phy_pipe_clk = { .cbcr_reg = USB3_PHY_PIPE_CBCR, .bcr_reg = USB3PHY_PHY_BCR, .has_sibling = 1, static struct gate_clk gcc_usb3_phy_pipe_clk = { .en_reg = USB3_PHY_PIPE_CBCR, .en_mask = BIT(0), .delay_us = 50, .base = &virt_base, .c = { .dbg_name = "gcc_usb3_phy_pipe_clk", .ops = &clk_ops_branch, .ops = &clk_ops_gate, CLK_INIT(gcc_usb3_phy_pipe_clk.c), }, }; static struct reset_clk gcc_usb3phy_phy_reset = { .reset_reg = USB3PHY_PHY_BCR, .base = &virt_base, .c = { .dbg_name = "gcc_usb3phy_phy_reset", .ops = &clk_ops_rst, CLK_INIT(gcc_usb3phy_phy_reset.c), }, }; static struct branch_clk gcc_usb_hs_ahb_clk = { .cbcr_reg = USB_HS_AHB_CBCR, .has_sibling = 1, Loading Loading @@ -2832,6 +2842,7 @@ static struct clk_lookup gcc_clocks_8994_common[] = { CLK_LIST(gcc_usb30_sleep_clk), CLK_LIST(gcc_usb3_phy_aux_clk), CLK_LIST(gcc_usb3_phy_pipe_clk), CLK_LIST(gcc_usb3phy_phy_reset), CLK_LIST(gcc_usb_hs_ahb_clk), CLK_LIST(gcc_usb_hs_system_clk), CLK_LIST(gcc_usb_phy_cfg_ahb2phy_clk), Loading include/dt-bindings/clock/msm-clocks-8994.h +1 −0 Original line number Diff line number Diff line Loading @@ -266,6 +266,7 @@ #define clk_gcc_usb30_sleep_clk 0xd0b65c92 #define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 #define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 #define clk_gcc_usb3phy_phy_reset 0xb1a4f885 #define clk_gcc_usb_hs_ahb_clk 0x72ce8032 #define clk_gcc_usb_hs_system_clk 0xa11972e5 #define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e Loading Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -1403,9 +1403,10 @@ <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_gcc_usb3_phy_reset>, <&clock_gcc clk_gcc_usb3phy_phy_reset>, <&clock_gcc clk_usb_ss_phy_ldo>; clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset", "ldo_clk"; "phy_phy_reset", "ldo_clk"; }; dbm_1p5: dbm@f92f8000 { Loading
drivers/clk/qcom/clock-gcc-8994.c +16 −5 Original line number Diff line number Diff line Loading @@ -2484,18 +2484,28 @@ static struct branch_clk gcc_usb3_phy_aux_clk = { }, }; static struct branch_clk gcc_usb3_phy_pipe_clk = { .cbcr_reg = USB3_PHY_PIPE_CBCR, .bcr_reg = USB3PHY_PHY_BCR, .has_sibling = 1, static struct gate_clk gcc_usb3_phy_pipe_clk = { .en_reg = USB3_PHY_PIPE_CBCR, .en_mask = BIT(0), .delay_us = 50, .base = &virt_base, .c = { .dbg_name = "gcc_usb3_phy_pipe_clk", .ops = &clk_ops_branch, .ops = &clk_ops_gate, CLK_INIT(gcc_usb3_phy_pipe_clk.c), }, }; static struct reset_clk gcc_usb3phy_phy_reset = { .reset_reg = USB3PHY_PHY_BCR, .base = &virt_base, .c = { .dbg_name = "gcc_usb3phy_phy_reset", .ops = &clk_ops_rst, CLK_INIT(gcc_usb3phy_phy_reset.c), }, }; static struct branch_clk gcc_usb_hs_ahb_clk = { .cbcr_reg = USB_HS_AHB_CBCR, .has_sibling = 1, Loading Loading @@ -2832,6 +2842,7 @@ static struct clk_lookup gcc_clocks_8994_common[] = { CLK_LIST(gcc_usb30_sleep_clk), CLK_LIST(gcc_usb3_phy_aux_clk), CLK_LIST(gcc_usb3_phy_pipe_clk), CLK_LIST(gcc_usb3phy_phy_reset), CLK_LIST(gcc_usb_hs_ahb_clk), CLK_LIST(gcc_usb_hs_system_clk), CLK_LIST(gcc_usb_phy_cfg_ahb2phy_clk), Loading
include/dt-bindings/clock/msm-clocks-8994.h +1 −0 Original line number Diff line number Diff line Loading @@ -266,6 +266,7 @@ #define clk_gcc_usb30_sleep_clk 0xd0b65c92 #define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 #define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 #define clk_gcc_usb3phy_phy_reset 0xb1a4f885 #define clk_gcc_usb_hs_ahb_clk 0x72ce8032 #define clk_gcc_usb_hs_system_clk 0xa11972e5 #define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e Loading