+5
−1
Loading
Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more
Implement the Recv ReqSeqAndFBit event when a RR frame with F bit set is received. Signed-off-by:Gustavo F. Padovan <gustavo@las.ic.unicamp.br> Signed-off-by:
Marcel Holtmann <marcel@holtmann.org>