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Commit ca0f1c3d authored by Subhash Jadavani's avatar Subhash Jadavani
Browse files

scsi: ufs-qcom: write the clock registers only if there is a change 



If we write REG_UFS_SYS1CLK_1US & REG_UFS_TX_SYMBOL_CLK_NS_US registers
multiple times (especially when UFS symbol clocks are not running) then
it might make the HW to go back to default value of these registers.
This change updates above registers only if there is a change in these
registers value.

Change-Id: I7c94c477e52b36b26a1624fa3ddfa75a49916d58
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent e4d39e9e

drivers/scsi/ufs/ufs-qcom.c

+19 −4
Original line number Diff line number Diff line
@@ -371,7 +371,14 @@ ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate) 
		core_clk_rate = DEFAULT_CLK_RATE_HZ;



	core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;

	if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {

		ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);

		/*

		 * make sure above write gets applied before we return from

		 * this function.

		 */

		mb();

	}



	core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;

	core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
@@ -421,9 +428,17 @@ ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate) 
		goto out_error;

	}



	if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=

	    (core_clk_period_in_ns | tx_clk_cycles_per_us)) {

		/* this register 2 fields shall be written at once */

		ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,

			      REG_UFS_TX_SYMBOL_CLK_NS_US);

		/*

		 * make sure above write gets applied before we return from

		 * this function.

		 */

		mb();

	}

	goto out;



out_error: