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Commit ca05fea6 authored by Natalie Protasevich's avatar Natalie Protasevich Committed by Linus Torvalds
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[PATCH] Do not enforce unique IO_APIC_ID check for xAPIC systems (i386) 



This patch is per Andi's request to remove NO_IOAPIC_CHECK from genapic and
use heuristics to prevent unique I/O APIC ID check for systems that don't
need it.  The patch disables unique I/O APIC ID check for Xeon-based and
other platforms that don't use serial APIC bus for interrupt delivery.
Andi stated that AMD systems don't need unique IO_APIC_IDs either.

Signed-off-by: default avatarNatalie Protasevich <Natalie.Protasevich@unisys.com>
Cc: Andi Kleen <ak@muc.de>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 7c1def16

arch/i386/kernel/io_apic.c

+6 −4
Original line number Diff line number Diff line
@@ -1658,6 +1658,12 @@ static void __init setup_ioapic_ids_from_mpc(void) 
	unsigned char old_id;

	unsigned long flags;



	/*

	 * Don't check I/O APIC IDs for xAPIC systems.  They have

	 * no meaning without the serial APIC bus.

	 */

	if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))

		return;

	/*

	 * This is broken; anything with a real cpu count has to

	 * circumvent this idiocy regardless.
@@ -1684,10 +1690,6 @@ static void __init setup_ioapic_ids_from_mpc(void) 
			mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;

		}



		/* Don't check I/O APIC IDs for some xAPIC systems.  They have

		 * no meaning without the serial APIC bus. */

		if (NO_IOAPIC_CHECK)

			continue;

		/*

		 * Sanity check, is the ID really free? Every APIC in a

		 * system must have a unique ID or we get lots of nice

arch/i386/kernel/mpparse.c

+4 −1
Original line number Diff line number Diff line
@@ -914,7 +914,10 @@ void __init mp_register_ioapic ( 
	mp_ioapics[idx].mpc_apicaddr = address;



	set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);

	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 < 15))

		mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);

	else

		mp_ioapics[idx].mpc_apicid = id;

	mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);

	

	/*

include/asm-i386/genapic.h

+0 −1
Original line number Diff line number Diff line
@@ -78,7 +78,6 @@ struct genapic { 
	.int_delivery_mode = INT_DELIVERY_MODE, \

	.int_dest_mode = INT_DEST_MODE, \

	.no_balance_irq = NO_BALANCE_IRQ, \

	.no_ioapic_check = NO_IOAPIC_CHECK, \

	.ESR_DISABLE = esr_disable, \

	.apic_destination_logical = APIC_DEST_LOGICAL, \

	APICFUNC(apic_id_registered), \

include/asm-i386/mach-bigsmp/mach_apic.h

+0 −2
Original line number Diff line number Diff line
@@ -14,8 +14,6 @@ 
#define NO_BALANCE_IRQ (1)

#define esr_disable (1)



#define NO_IOAPIC_CHECK (0)



static inline int apic_id_registered(void)

{

	return (1);

include/asm-i386/mach-default/mach_apic.h

+0 −2
Original line number Diff line number Diff line
@@ -19,8 +19,6 @@ static inline cpumask_t target_cpus(void) 
#define NO_BALANCE_IRQ (0)

#define esr_disable (0)



#define NO_IOAPIC_CHECK (0)



#define INT_DELIVERY_MODE dest_LowestPrio

#define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */