Merge "msm: ipa: Add support for RNDIS in IPA driver" (c9b6f19b) · Commits · e / devices / android_kernel_sony_msm8994

arch/arm/mach-msm/include/mach/ipa.h

+86 −0

Original line number	Diff line number	Diff line
		@@ -83,6 +83,17 @@ enum ipa_dp_evt_type {
		IPA_WRITE_DONE,
		};

		/**
		* enum hdr_total_len_or_pad_type - type vof alue held by TOTAL_LEN_OR_PAD
		* field in header configuration register.
		* @IPA_HDR_PAD: field is used as padding length
		* @IPA_HDR_TOTAL_LEN: field is used as total length
		*/
		enum hdr_total_len_or_pad_type {
		IPA_HDR_PAD = 0,
		IPA_HDR_TOTAL_LEN = 1,
		};

		/**
		* struct ipa_ep_cfg_nat - NAT configuration in IPA end-point
		* @nat_en: This defines the default NAT mode for the pipe: in case of
		@@ -150,6 +161,33 @@ struct ipa_ep_cfg_hdr {
		u32 hdr_metadata_reg_valid;
		};

		/**
		* struct ipa_ep_cfg_hdr_ext - extended header configuration in IPA end-point
		* @hdr_pad_to_alignment: Pad packet to specified alignment
		* (2^pad to alignment value), i.e. value of 3 means pad to 2^3 = 8 bytes
		* alignment. Alignment is to 0,2 up to 32 bytes (IPAv2 does not support 64
		* byte alignment). Valid for Output Pipes only (IPA Producer).
		* @hdr_total_len_or_pad_offset: Offset to length field containing either
		* total length or pad length, per hdr_total_len_or_pad config
		* @hdr_payload_len_inc_padding: 0-IPA_ENDP_INIT_HDR_n’s HDR_OFST_PKT_SIZE does
		* not includes padding bytes size, payload_len = packet length,
		* 1-IPA_ENDP_INIT_HDR_n’s HDR_OFST_PKT_SIZE includes
		* padding bytes size, payload_len = packet length + padding
		* @hdr_total_len_or_pad: field is used as PAD length ot as Total length
		* (header + packet + padding)
		* @hdr_total_len_or_pad_valid: 0-Ignore TOTAL_LEN_OR_PAD field, 1-Process
		* TOTAL_LEN_OR_PAD field
		* @hdr_little_endian: 0-Big Endian, 1-Little Endian
		*/
		struct ipa_ep_cfg_hdr_ext {
		u32 hdr_pad_to_alignment;
		u32 hdr_total_len_or_pad_offset;
		bool hdr_payload_len_inc_padding;
		enum hdr_total_len_or_pad_type hdr_total_len_or_pad;
		bool hdr_total_len_or_pad_valid;
		bool hdr_little_endian;
		};

		/**
		* struct ipa_ep_cfg_mode - mode configuration in IPA end-point
		* @mode: Valid for Input Pipes only (IPA Consumer)
		@@ -181,12 +219,20 @@ struct ipa_ep_cfg_mode {
		* there is no aggregation, every packet is sent
		* independently according to the aggregation structure
		* Valid for Output Pipes only (IPA Producer)
		* @aggr_pkt_limit: Defines if EOF close aggregation or not. if set to false
		* HW closes aggregation (sends EOT) only based on its
		* aggregation config (byte/time limit, etc). if set to
		* true EOF closes aggregation in addition to HW based
		* aggregation closure. Valid for Output Pipes only (IPA
		* Producer). EOF affects only Pipes configured for
		* generic aggregation.
		*/
		struct ipa_ep_cfg_aggr {
		enum ipa_aggr_en_type aggr_en;
		enum ipa_aggr_type aggr;
		u32 aggr_byte_limit;
		u32 aggr_time_limit;
		u32 aggr_pkt_limit;
		};

		/**
		@@ -211,19 +257,41 @@ struct ipa_ep_cfg_holb {
		u16 tmr_val;
		};

		/**
		* struct ipa_ep_cfg_deaggr - deaggregation configuration in IPA end-point
		* @deaggr_hdr_len: Deaggregation Header length in bytes. Valid only for Input
		* Pipes, which are configured for ’Generic’ deaggregation.
		* @packet_offset_valid: - 0: PACKET_OFFSET is not used, 1: PACKET_OFFSET is
		* used.
		* @packet_offset_location: Location of packet offset field, which specifies
		* the offset to the packet from the start of the packet offset field.
		* @max_packet_len: DEAGGR Max Packet Length in Bytes. A Packet with higher
		* size wil be treated as an error. 0 - Packet Length is not Bound,
		* IPA should not check for a Max Packet Length.
		*/
		struct ipa_ep_cfg_deaggr {
		u32 deaggr_hdr_len;
		bool packet_offset_valid;
		u32 packet_offset_location;
		u32 max_packet_len;
		};

		/**
		* struct ipa_ep_cfg - configuration of IPA end-point
		* @nat: NAT parmeters
		* @hdr: Header parameters
		* @mode: Mode parameters
		* @aggr: Aggregation parameters
		* @deaggr: Deaggregation params
		* @route: Routing parameters
		*/
		struct ipa_ep_cfg {
		struct ipa_ep_cfg_nat nat;
		struct ipa_ep_cfg_hdr hdr;
		struct ipa_ep_cfg_hdr_ext hdr_ext;
		struct ipa_ep_cfg_mode mode;
		struct ipa_ep_cfg_aggr aggr;
		struct ipa_ep_cfg_deaggr deaggr;
		struct ipa_ep_cfg_route route;
		};

		@@ -519,10 +587,16 @@ int ipa_cfg_ep_nat(u32 clnt_hdl, const struct ipa_ep_cfg_nat *ipa_ep_cfg);

		int ipa_cfg_ep_hdr(u32 clnt_hdl, const struct ipa_ep_cfg_hdr *ipa_ep_cfg);

		int ipa_cfg_ep_hdr_ext(u32 clnt_hdl,
		const struct ipa_ep_cfg_hdr_ext *ipa_ep_cfg);

		int ipa_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ipa_ep_cfg);

		int ipa_cfg_ep_aggr(u32 clnt_hdl, const struct ipa_ep_cfg_aggr *ipa_ep_cfg);

		int ipa_cfg_ep_deaggr(u32 clnt_hdl,
		const struct ipa_ep_cfg_deaggr *ipa_ep_cfg);

		int ipa_cfg_ep_route(u32 clnt_hdl, const struct ipa_ep_cfg_route *ipa_ep_cfg);

		int ipa_cfg_ep_holb(u32 clnt_hdl, const struct ipa_ep_cfg_holb *ipa_ep_cfg);
		@@ -793,6 +867,12 @@ static inline int ipa_cfg_ep_hdr(u32 clnt_hdl,
		return -EPERM;
		}

		static inline int ipa_cfg_ep_hdr_ext(u32 clnt_hdl,
		const struct ipa_ep_cfg_hdr_ext *ipa_ep_cfg)
		{
		return -EPERM;
		}

		static inline int ipa_cfg_ep_mode(u32 clnt_hdl,
		const struct ipa_ep_cfg_mode *ipa_ep_cfg)
		{
		@@ -805,6 +885,12 @@ static inline int ipa_cfg_ep_aggr(u32 clnt_hdl,
		return -EPERM;
		}

		static inline int ipa_cfg_ep_deaggr(u32 clnt_hdl,
		const struct ipa_ep_cfg_deaggr *ipa_ep_cfg)
		{
		return -EPERM;
		}

		static inline int ipa_cfg_ep_route(u32 clnt_hdl,
		const struct ipa_ep_cfg_route *ipa_ep_cfg)
		{

drivers/platform/msm/ipa/ipa_debugfs.c

+32 −26

Original line number	Diff line number	Diff line
		@@ -304,19 +304,24 @@ int _ipa_read_ep_reg_v1_1(char *buf, int max_len, int pipe)

		int _ipa_read_ep_reg_v2_0(char *buf, int max_len, int pipe)
		{
		return scnprintf(dbg_buff, IPA_MAX_MSG_LEN,
		return scnprintf(
		dbg_buff, IPA_MAX_MSG_LEN,
		"IPA_ENDP_INIT_NAT_%u=0x%x\n"
		"IPA_ENDP_INIT_HDR_%u=0x%x\n"
		"IPA_ENDP_INIT_HDR_EXT_%u=0x%x\n"
		"IPA_ENDP_INIT_MODE_%u=0x%x\n"
		"IPA_ENDP_INIT_AGGR_%u=0x%x\n"
		"IPA_ENDP_INIT_ROUTE_%u=0x%x\n"
		"IPA_ENDP_INIT_CTRL_%u=0x%x\n"
		"IPA_ENDP_INIT_HOL_EN_%u=0x%x\n"
		"IPA_ENDP_INIT_HOL_TIMER_%u=0x%x\n",
		"IPA_ENDP_INIT_HOL_TIMER_%u=0x%x\n"
		"IPA_ENDP_INIT_DEAGGR_%u=0x%x\n",
		pipe, ipa_read_reg(ipa_ctx->mmio,
		IPA_ENDP_INIT_NAT_N_OFST_v2_0(pipe)),
		pipe, ipa_read_reg(ipa_ctx->mmio,
		IPA_ENDP_INIT_HDR_N_OFST_v2_0(pipe)),
		pipe, ipa_read_reg(ipa_ctx->mmio,
		IPA_ENDP_INIT_HDR_EXT_n_OFST_v2_0(pipe)),
		pipe, ipa_read_reg(ipa_ctx->mmio,
		IPA_ENDP_INIT_MODE_N_OFST_v2_0(pipe)),
		pipe, ipa_read_reg(ipa_ctx->mmio,
		@@ -328,8 +333,9 @@ int _ipa_read_ep_reg_v2_0(char *buf, int max_len, int pipe)
		pipe, ipa_read_reg(ipa_ctx->mmio,
		IPA_ENDP_INIT_HOL_BLOCK_EN_N_OFST_v2_0(pipe)),
		pipe, ipa_read_reg(ipa_ctx->mmio,
		IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v2_0(pipe))
		);
		IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v2_0(pipe)),
		pipe, ipa_read_reg(ipa_ctx->mmio,
		IPA_ENDP_INIT_DEAGGR_n_OFST_v2_0(pipe)));
		}

		static ssize_t ipa_read_ep_reg(struct file file, char __user ubuf,

drivers/platform/msm/ipa/ipa_hdr.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -12,7 +12,7 @@

		#include "ipa_i.h"

		static const u32 ipa_hdr_bin_sz[IPA_HDR_BIN_MAX] = { 8, 16, 24, 36 };
		static const u32 ipa_hdr_bin_sz[IPA_HDR_BIN_MAX] = { 8, 16, 24, 36, 58};

		/**
		* ipa_generate_hdr_hw_tbl() - generates the headers table
		@@ -178,6 +178,8 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr)
		bin = IPA_HDR_BIN2;
		else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN3])
		bin = IPA_HDR_BIN3;
		else if (hdr->hdr_len <= ipa_hdr_bin_sz[IPA_HDR_BIN4])
		bin = IPA_HDR_BIN4;
		else {
		IPAERR("unexpected hdr len %d\n", hdr->hdr_len);
		goto bad_hdr_len;

drivers/platform/msm/ipa/ipa_i.h

+6 −1

Original line number	Diff line number	Diff line
		@@ -104,7 +104,8 @@
		#define IPA_HDR_BIN1 1
		#define IPA_HDR_BIN2 2
		#define IPA_HDR_BIN3 3
		#define IPA_HDR_BIN_MAX 4
		#define IPA_HDR_BIN4 4
		#define IPA_HDR_BIN_MAX 5

		#define IPA_EVENT_THRESHOLD 0x10

		@@ -793,8 +794,12 @@ struct ipa_controller {
		void (*ipa_sram_read_settings)(void);
		void (*ipa_cfg_ep_hdr)(u32 pipe_number,
		const struct ipa_ep_cfg_hdr *ipa_ep_hdr_cfg);
		int (*ipa_cfg_ep_hdr_ext)(u32 pipe_number,
		const struct ipa_ep_cfg_hdr_ext *ipa_ep_hdr_ext_cfg);
		void (*ipa_cfg_ep_aggr)(u32 pipe_number,
		const struct ipa_ep_cfg_aggr *ipa_ep_agrr_cfg);
		int (*ipa_cfg_ep_deaggr)(u32 pipe_index,
		const struct ipa_ep_cfg_deaggr *ep_deaggr);
		void (*ipa_cfg_ep_nat)(u32 pipe_number,
		const struct ipa_ep_cfg_nat *ipa_ep_nat_cfg);
		void (*ipa_cfg_ep_mode)(u32 pipe_number, u32 dst_pipe_number,

drivers/platform/msm/ipa/ipa_reg.h

+26 −0

Original line number	Diff line number	Diff line
		@@ -122,6 +122,8 @@ Common Registers
		#define IPA_ENDP_INIT_NAT_N_NAT_EN_SHFT 0x0
		#define IPA_COMP_CFG_OFST 0x00000038

		#define IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK 0x1f8000
		#define IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT 0xf
		#define IPA_ENDP_INIT_AGGR_N_AGGR_TIME_LIMIT_BMSK 0x7c00
		#define IPA_ENDP_INIT_AGGR_N_AGGR_TIME_LIMIT_SHFT 0xa
		#define IPA_ENDP_INIT_AGGR_N_AGGR_BYTE_LIMIT_BMSK 0x3e0
		@@ -172,6 +174,20 @@ Common Registers
		#define IPA_ENDP_INIT_NAT_N_NAT_EN_SHFT 0x0


		#define IPA_ENDP_INIT_HDR_EXT_n_OFST_v2_0(n) (0x000001c0 + 0x4 * (n))
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANESS_BMSK 0x1
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_ENDIANESS_SHFT 0x0
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK 0x2
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_SHFT 0x1
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_BMSK 0x4
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_SHFT 0x2
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_BMSK 0x8
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_SHFT 0x3
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK 0x3f0
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT 0x4
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK 0x1c00
		#define IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT 0xa


		/*
		IPA HW 1.1 specific Registers
		@@ -197,6 +213,16 @@ Common Registers
		#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_EN_BMSK 0x1
		#define IPA_ENDP_INIT_HOL_BLOCK_EN_N_EN_SHFT 0x0

		#define IPA_ENDP_INIT_DEAGGR_n_OFST_v2_0(n) (0x00000470 + 0x04 * (n))
		#define IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK 0x3F
		#define IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT 0x0
		#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK 0x40
		#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT 0x6
		#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK 0x3F00
		#define IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT 0x8
		#define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xFFFF0000
		#define IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT 0x10

		#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v1_1(n) (0x000002c0 + 0x4 * (n))
		#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_OFST_v2_0(n) (0x00000420 + 0x4 * (n))
		#define IPA_ENDP_INIT_HOL_BLOCK_TIMER_N_RMSK 0x1ff