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Commit c7867fe2 authored by Dhaval Patel's avatar Dhaval Patel
Browse files

clk: qcom: mdss: Fix MDSS HDMI pll support 



PHY registers are not updated during MDSS HDMI
pll configuration due to wrong memory mapping.
It also leads to crash when user connects the
HDMI cable with target. This change fixes the
memory mapping for PHY and also adds the missing
register configuration entry for HDMI pll.

Change-Id: Ie81045fed320993fbab6b02bec6b2b82e5b5d495
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 526b8cba

drivers/clk/qcom/mdss/mdss-hdmi-pll-28hpm.c

+1 −0
Original line number Diff line number Diff line
@@ -509,6 +509,7 @@ static int hdmi_vco_set_rate(struct clk *c, unsigned long rate) 
		MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);

		MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);

		MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x02);

		MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x00);

		MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);

		MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);

		MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);

drivers/clk/qcom/mdss/mdss-pll.c

+2 −2
Original line number Diff line number Diff line
@@ -226,8 +226,8 @@ static int mdss_pll_probe(struct platform_device *pdev) 
			goto phy_io_error;

		}

	} else {

		pll_res->phy_base = ioremap(pll_base_reg->start,

						resource_size(pll_base_reg));

		pll_res->phy_base = ioremap(phy_base_reg->start,

						resource_size(phy_base_reg));

		if (!pll_res->phy_base) {

			pr_err("Unable to remap pll phy base resources\n");

			rc = -ENOMEM;