Merge "Revert "ARM: gic: Patches for 8625 hardware workaround"" (c655c31f) · Commits · e / devices / android_kernel_sony_msm8994

drivers/irqchip/irq-gic.c

+1 −150

Original line number	Diff line number	Diff line
		@@ -216,14 +216,8 @@ static int gic_suspend_one(struct gic_chip_data *gic)
		{
		unsigned int i;
		void __iomem *base = gic_data_dist_base(gic);
		#ifdef CONFIG_ARCH_MSM8625
		unsigned long flags;
		#endif

		for (i = 0; i * 32 < gic->gic_irqs; i++) {
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_lock_irqsave(&irq_controller_lock, flags);
		#endif
		gic->enabled_irqs[i]
		= readl_relaxed(base + GIC_DIST_ENABLE_SET + i * 4);
		/* disable all of them */
		@@ -231,9 +225,6 @@ static int gic_suspend_one(struct gic_chip_data *gic)
		/* enable the wakeup set */
		writel_relaxed(gic->wakeup_irqs[i],
		base + GIC_DIST_ENABLE_SET + i * 4);
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
		#endif
		}
		mb();
		return 0;
		@@ -259,7 +250,6 @@ static void gic_show_resume_irq(struct gic_chip_data *gic)
		if (!msm_show_resume_irq_mask)
		return;

		raw_spin_lock(&irq_controller_lock);
		for (i = 0; i * 32 < gic->gic_irqs; i++) {
		enabled = readl_relaxed(base + GIC_DIST_ENABLE_CLEAR + i * 4);
		pending[i] = readl_relaxed(base + GIC_DIST_PENDING_SET + i * 4);
		@@ -287,7 +277,6 @@ static void gic_resume_one(struct gic_chip_data *gic)
		{
		unsigned int i;
		void __iomem *base = gic_data_dist_base(gic);

		gic_show_resume_irq(gic);
		for (i = 0; i * 32 < gic->gic_irqs; i++) {
		/* disable all of them */
		@@ -327,13 +316,8 @@ static void gic_eoi_irq(struct irq_data *d)
		gic_arch_extn.irq_eoi(d);
		raw_spin_unlock(&irq_controller_lock);
		}
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_lock(&irq_controller_lock);
		#endif

		writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_unlock(&irq_controller_lock);
		#endif
		}

		static int gic_set_type(struct irq_data *d, unsigned int type)
		@@ -453,13 +437,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
		void __iomem *cpu_base = gic_data_cpu_base(gic);

		do {
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_lock(&irq_controller_lock);
		#endif
		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_unlock(&irq_controller_lock);
		#endif
		irqnr = irqstat & ~0x1c00;

		if (likely(irqnr > 15 && irqnr < 1021)) {
		@@ -468,13 +446,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
		continue;
		}
		if (irqnr < 16) {
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_lock(&irq_controller_lock);
		#endif
		writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_unlock(&irq_controller_lock);
		#endif
		#ifdef CONFIG_SMP
		handle_IPI(irqnr, regs);
		#endif
		@@ -631,9 +603,6 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
		* Deal with the banked PPI and SGI interrupts - disable all
		* PPI interrupts, ensure all SGI interrupts are enabled.
		*/
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_lock(&irq_controller_lock);
		#endif
		writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
		writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);

		@@ -653,9 +622,6 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
		writel_relaxed(0xF, base + GIC_CPU_CTRL);
		else
		writel_relaxed(1, base + GIC_CPU_CTRL);
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_unlock(&irq_controller_lock);
		#endif
		mb();
		}

		@@ -867,9 +833,6 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
		int cpu;
		unsigned long sgir;
		unsigned long map = 0;
		#ifdef CONFIG_ARCH_MSM8625
		unsigned long flags;
		#endif

		/* Convert our logical CPU mask into a physical one. */
		for_each_cpu(cpu, mask)
		@@ -884,15 +847,9 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
		*/
		dsb();

		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_lock_irqsave(&irq_controller_lock, flags);
		#endif
		/* this always happens on GIC0 */
		writel_relaxed(sgir,
		gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
		#ifdef CONFIG_ARCH_MSM8625
		raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
		#endif
		mb();
		}
		#endif
		@@ -1165,109 +1122,3 @@ void gic_clear_irq_pending(unsigned int irq)
		GIC_DIST_PENDING_CLEAR + (gic_irq(d) / 32) * 4);
		raw_spin_unlock(&irq_controller_lock);
		}

		#ifdef CONFIG_ARCH_MSM8625
		/*
		* Check for any interrupts which are enabled are pending
		* in the pending set or not.
		* Return :
		* 0 : No pending interrupts
		* 1 : Pending interrupts other than A9_M2A_5
		*/
		unsigned int msm_gic_spi_ppi_pending(void)
		{
		unsigned int i, bit = 0;
		unsigned int pending_enb = 0, pending = 0;
		unsigned long value = 0;
		struct gic_chip_data *gic = &gic_data[0];
		void __iomem *base = gic_data_dist_base(gic);
		unsigned long flags;

		raw_spin_lock_irqsave(&irq_controller_lock, flags);
		/*
		* PPI and SGI to be included.
		* MSM8625_INT_A9_M2A_5 needs to be ignored, as A9_M2A_5
		* requesting sleep triggers it
		*/
		for (i = 0; (i * 32) < gic->gic_irqs; i++) {
		pending = readl_relaxed(base +
		GIC_DIST_PENDING_SET + i * 4);
		pending_enb = readl_relaxed(base +
		GIC_DIST_ENABLE_SET + i * 4);
		value = pending & pending_enb;

		if (value) {
		for (bit = 0; bit < 32; bit++) {
		bit = find_next_bit(&value, 32, bit);
		if ((bit + 32 * i) != MSM8625_INT_A9_M2A_5) {
		raw_spin_unlock_irqrestore(
		&irq_controller_lock, flags);
		return 1;
		}
		}
		}
		}
		raw_spin_unlock_irqrestore(&irq_controller_lock, flags);

		return 0;
		}

		void msm_gic_save(bool modem_wake, int from_idle)
		{
		unsigned int i;
		struct gic_chip_data *gic = &gic_data[0];
		void __iomem *base = gic_data_dist_base(gic);

		gic_cpu_save(0);
		gic_dist_save(0);
		/* Disable all the Interrupts, before we enter pc */
		for (i = 0; (i * 32) < gic->gic_irqs; i++) {
		raw_spin_lock(&irq_controller_lock);
		writel_relaxed(0xffffffff, base
		+ GIC_DIST_ENABLE_CLEAR + i * 4);
		raw_spin_unlock(&irq_controller_lock);
		}
		}

		void msm_gic_restore(void)
		{
		gic_dist_restore(0);
		gic_cpu_restore(0);
		}

		/*
		* Configure the GIC after we come out of power collapse.
		* This function will configure some of the GIC registers so as to prepare the
		* secondary cores to receive an SPI(ACSR_MP_CORE_IPC1/IPC2/IPC3, 40/92/93),
		* which will bring cores out of GDFS.
		*/
		void gic_configure_and_raise(unsigned int irq, unsigned int cpu)
		{
		struct gic_chip_data *gic = &gic_data[0];
		struct irq_data *d = irq_get_irq_data(irq);
		void __iomem *base = gic_data_dist_base(gic);
		unsigned int value = 0, byte_offset, offset, bit;
		unsigned long flags;

		offset = ((gic_irq(d) / 32) * 4);
		bit = BIT(gic_irq(d) % 32);

		raw_spin_lock_irqsave(&irq_controller_lock, flags);

		value = __raw_readl(base + GIC_DIST_ACTIVE_SET + offset);
		__raw_writel(value \| bit, base + GIC_DIST_ACTIVE_SET + offset);
		mb();

		value = __raw_readl(base + GIC_DIST_TARGET + (gic_irq(d) / 4) * 4);
		byte_offset = (gic_irq(d) % 4) * 8;
		value \|= 1 << (cpu + byte_offset);
		__raw_writel(value, base + GIC_DIST_TARGET + (gic_irq(d) / 4) * 4);
		mb();

		value = __raw_readl(base + GIC_DIST_ENABLE_SET + offset);
		__raw_writel(value \| bit, base + GIC_DIST_ENABLE_SET + offset);
		mb();

		raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
		}
		#endif

include/linux/irqchip/arm-gic.h

+4 −6

Original line number	Diff line number	Diff line
		@@ -79,10 +79,8 @@ static inline void gic_init(unsigned int nr, int start,
		gic_init_bases(nr, start, dist, cpu, 0, NULL);
		}

		#ifdef CONFIG_ARCH_MSM8625
		void msm_gic_save(bool modem_wake, int from_idle);
		void msm_gic_restore(void);
		void gic_configure_and_raise(unsigned int irq, unsigned int cpu);
		#endif
		#endif
		bool gic_is_spi_pending(unsigned int irq);
		void gic_clear_spi_pending(unsigned int irq);

		#endif /* __ASSEMBLY */
		#endif