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Commit c59faa2d authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add MDSS devices for msmplutonium"

parents 40a16350 a5cac836

Documentation/devicetree/bindings/fb/mdss-mdp.txt

+12 −3
Original line number Diff line number Diff line
@@ -30,7 +30,10 @@ Required properties 
- qcom,mdss-pipe-vig-clk-ctrl-off: Array of offsets describing clk control

				offsets for dynamic clock gating. 1st value

				in the array represents offset of the control

				register. 2nd value represents bit offset within

				register. The offsets are calculated from

				"mdp_phys" + mdp-reg-offset that are defined

				in reg property and mdss-mdp-reg-offset respectively.

				2nd value represents bit offset within

				control register and 3rd value represents bit

				offset within status register. Number of tuples

				defined should match the number of offsets
@@ -53,7 +56,10 @@ Required properties 
- qcom,mdss-pipe-rgb-clk-ctrl-off: Array of offsets describing clk control

				offsets for dynamic clock gating. 1st value

				in the array represents offset of the control

				register. 2nd value represents bit offset within

				register. The offsets are calculated from

				"mdp_phys" + mdp-reg-offset that are defined

				in reg property and mdss-mdp-reg-offset respectively.

				2nd value represents bit offset within

				control register and 3rd value represents bit

				offset within status register. Number of tuples

				defined should match the number of offsets
@@ -76,7 +82,10 @@ Required properties 
- qcom,mdss-pipe-dma-clk-ctrl-off: Array of offsets describing clk control

				offsets for dynamic clock gating. 1st value

				in the array represents offset of the control

				register. 2nd value represents bit offset within

				register. The offsets are calculated from

				"mdp_phys" + mdp-reg-offset that are defined

				in reg property and mdss-mdp-reg-offset respectively.

				2nd value represents bit offset within

				control register and 3rd value represents bit

				offset within status register. Number of tuples

				defined should match the number of offsets

arch/arm/boot/dts/qcom/msmplutonium-mdss.dtsi

0 → 100644
+146 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2014 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	mdss_mdp: qcom,mdss_mdp@fd900000 {

		compatible = "qcom,mdss_mdp";

		reg = <0xfd900000 0x90000>,

		      <0xfd9c8000 0x1000>;

		reg-names = "mdp_phys", "vbif_phys";

		interrupts = <0 83 0>;

		vdd-supply = <&gdsc_mdss>;



		/* Bus Scale Settings */

		qcom,msm-bus,name = "mdss_mdp";

		qcom,msm-bus,num-cases = <3>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

			<22 512 0 0>, <23 512 0 0>,

			<22 512 0 6400000>, <23 512 0 6400000>,

			<22 512 0 6400000>, <23 512 0 6400000>;



		/* Fudge factors */

		qcom,mdss-ab-factor = <2 1>;		/* 2 times    */

		qcom,mdss-ib-factor = <6 5>;		/* 1.2 times  */

		qcom,mdss-clk-factor = <105 100>;	/* 1.05 times */



		qcom,mdss-mdp-reg-offset = <0x00001000>;

		qcom,max-bandwidth-low-kbps = <6000000>;

		qcom,max-bandwidth-high-kbps = <6000000>;

		qcom,max-bandwidth-per-pipe-kbps = <1650000>;

		qcom,max-clk-rate = <400000000>;



		qcom,mdss-pipe-vig-off = <0x00005000 0x00007000

					  0x00009000 0x0000B000>;

		qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000

					  0x00019000 0x0001B000>;

		qcom,mdss-pipe-dma-off = <0x00025000 0x00027000>;



		qcom,mdss-pipe-vig-fetch-id = <1 4 7 19>;

		qcom,mdss-pipe-rgb-fetch-id = <16 17 18 22>;

		qcom,mdss-pipe-dma-fetch-id = <10 13>;



		qcom,mdss-pipe-vig-xin-id = <0 4 8 12>;

		qcom,mdss-pipe-rgb-xin-id = <1 5 9 13>;

		qcom,mdss-pipe-dma-xin-id = <2 10>;



		/* TODO: Need to add fixed mmb for VIG */

		qcom,mdss-pipe-rgb-fixed-mmb =	<5 0 1 8 9 10>,

						<5 2 3 11 12 13>,

						<5 4 5 14 15 16>,

						<5 6 7 17 18 19>;



		/* These Offsets are relative to "mdp_phys + mdp-reg-offset" address */

		qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2AC 0 0>,

						      <0x2B4 0 0>,

						      <0x2BC 0 0>,

						      <0x2C4 0 0>;

		qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2AC 4 8>,

						      <0x2B4 4 8>,

						      <0x2BC 4 8>,

						      <0x2C4 4 8>;

		qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>,

						      <0x2B4 8 12>;



		qcom,mdss-pipe-sw-reset-off = <0x0028>;

		qcom,mdss-pipe-vig-sw-reset-map = <5 6 7 8>;

		qcom,mdss-pipe-rgb-sw-reset-map = <9 10 11 12>;

		qcom,mdss-pipe-dma-sw-reset-map = <13 14>;



		qcom,mdss-smp-data = <44 8192>;

		qcom,mdss-sspp-len = <0x00002000>;



		qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400

				     0x00002600 0x00002800>;

		qcom,mdss-mixer-intf-off = <0x00045000 0x00046000

					    0x00047000 0x0004A000>;

		qcom,mdss-mixer-wb-off = <0x00048000 0x00049000>;

		qcom,mdss-dspp-off = <0x00055000 0x00057000 0x00059000

				      0x0005B000>;

		qcom,mdss-wb-off = <0x00065000 0x00065800 0x00066000

				    0x00066800 0x00067000>;

		qcom,mdss-intf-off = <0x0006B000 0x0006B800 0x0006C000

				      0x0006C800 0x0006D000>;

		qcom,mdss-pingpong-off = <0x00071000 0x00071800 0x00072000

					  0x00072800>;

		qcom,mdss-wfd-mode = "intf";

		qcom,mdss-ctl-len = <0x00000200>;



		clocks = <&clock_mmss clk_mdss_ahb_clk>,

			 <&clock_mmss clk_mdss_axi_clk>,

			 <&clock_mmss clk_mdp_clk_src>,

			 <&clock_mmss clk_mdss_mdp_clk>,

			 <&clock_mmss clk_mdss_vsync_clk>;

		clock-names = "iface_clk", "bus_clk", "core_clk_src",

				"core_clk", "vsync_clk";



		/* These Offsets are relative to "mdp_phys" address */

		qcom,mdp-settings = <0x011E0 0x000000A9>,

				    <0x011E4 0x00000055>,

				    <0x012AC 0xC0000CCC>,

				    <0x012B4 0xC0000CCC>,

				    <0x012BC 0x00CCCCCC>,

				    <0x012C4 0x000000CC>,

				    <0x013A8 0x0CCCC0C0>,

				    <0x013B0 0xCCCCC0C0>,

				    <0x013B8 0xCCCCC0C0>,

				    <0x013D0 0x00CCC000>,

				    <0x65048 0x00000058>,

				    <0x65848 0x00000058>,

				    <0x66048 0x00000058>,

				    <0x66848 0x00000058>,

				    <0x67048 0x00000058>;



		/* buffer parameters to calculate prefill bandwidth */

		/* TODO: Need to check BW settings */

		qcom,mdss-prefill-outstanding-buffer-bytes = <1024>;

		qcom,mdss-prefill-y-buffer-bytes = <4096>;

		qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;

		qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;

		qcom,mdss-prefill-post-scaler-buffer-pixels = <2048>;

		qcom,mdss-prefill-pingpong-buffer-pixels = <5120>;

		qcom,mdss-prefill-fbc-lines = <2>;



		mdss_fb0: qcom,mdss_fb_primary {

			cell-index = <0>;

			compatible = "qcom,mdss-fb";

			qcom,memblock-reserve = <0x03200000 0x01E00000>;

		};

	};



	qcom,mdss_wb_panel {

		compatible = "qcom,mdss_wb";

		qcom,mdss_pan_res = <640 480>;

		qcom,mdss_pan_bpp = <24>;

		qcom,mdss-fb-map = <&mdss_fb0>;

	};

};