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Commit c537cf50 authored by Krishna Chaitanya Parimi's avatar Krishna Chaitanya Parimi
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msm: mdss: Extend GC programming to writeback mixers in pp 



Currently pp_mixer_setup does not configure the gamma
correction in writeback mixers. Extending the function to
incorporate programming of writeback mixers as well.

Change-Id: I9c2ffa0153e642d603474965d6d0372dd6403685
Signed-off-by: default avatarKrishna Chaitanya Parimi <cparimi@codeaurora.org>
parent f1a9f6d4

drivers/video/msm/mdss/mdss_mdp_pp.c

+51 −24
Original line number Diff line number Diff line
@@ -80,6 +80,8 @@ struct mdp_csc_cfg mdp_csc_convert[MDSS_MDP_MAX_CSC] = { 
#define CSC_POST_OFF	0xC



#define MDSS_BLOCK_DISP_NUM	(MDP_BLOCK_MAX - MDP_LOGICAL_BLOCK_DISP_0)

#define MDSS_MAX_MIXER_DISP_NUM	(MDSS_BLOCK_DISP_NUM + \

			MDSS_MDP_WB_MAX_LAYERMIXER)



#define HIST_INTR_DSPP_MASK		0xFFF000

#define HIST_V2_INTR_BIT_MASK		0xF33000
@@ -300,15 +302,15 @@ static int mdss_mdp_hscl_filter[] = { 


struct mdss_pp_res_type {

	/* logical info */

	u32 pp_disp_flags[MDSS_BLOCK_DISP_NUM];

	u32 pp_disp_flags[MDSS_MAX_MIXER_DISP_NUM];

	u32 igc_lut_c0c1[MDSS_BLOCK_DISP_NUM][IGC_LUT_ENTRIES];

	u32 igc_lut_c2[MDSS_BLOCK_DISP_NUM][IGC_LUT_ENTRIES];

	struct mdp_ar_gc_lut_data

		gc_lut_r[MDSS_BLOCK_DISP_NUM][GC_LUT_SEGMENTS];

		gc_lut_r[MDSS_MAX_MIXER_DISP_NUM][GC_LUT_SEGMENTS];

	struct mdp_ar_gc_lut_data

		gc_lut_g[MDSS_BLOCK_DISP_NUM][GC_LUT_SEGMENTS];

		gc_lut_g[MDSS_MAX_MIXER_DISP_NUM][GC_LUT_SEGMENTS];

	struct mdp_ar_gc_lut_data

		gc_lut_b[MDSS_BLOCK_DISP_NUM][GC_LUT_SEGMENTS];

		gc_lut_b[MDSS_MAX_MIXER_DISP_NUM][GC_LUT_SEGMENTS];

	u32 enhist_lut[MDSS_BLOCK_DISP_NUM][ENHIST_LUT_ENTRIES];

	struct mdp_pa_cfg pa_disp_cfg[MDSS_BLOCK_DISP_NUM];

	struct mdp_pa_v2_data pa_v2_disp_cfg[MDSS_BLOCK_DISP_NUM];
@@ -316,7 +318,7 @@ struct mdss_pp_res_type { 
	u32 six_zone_lut_curve_p1[MDSS_BLOCK_DISP_NUM][MDP_SIX_ZONE_LUT_SIZE];

	struct mdp_pcc_cfg_data pcc_disp_cfg[MDSS_BLOCK_DISP_NUM];

	struct mdp_igc_lut_data igc_disp_cfg[MDSS_BLOCK_DISP_NUM];

	struct mdp_pgc_lut_data argc_disp_cfg[MDSS_BLOCK_DISP_NUM];

	struct mdp_pgc_lut_data argc_disp_cfg[MDSS_MAX_MIXER_DISP_NUM];

	struct mdp_pgc_lut_data pgc_disp_cfg[MDSS_BLOCK_DISP_NUM];

	struct mdp_hist_lut_data enhist_disp_cfg[MDSS_BLOCK_DISP_NUM];

	struct mdp_dither_cfg_data dither_disp_cfg[MDSS_BLOCK_DISP_NUM];
@@ -1373,7 +1375,7 @@ int mdss_mdp_pipe_sspp_setup(struct mdss_mdp_pipe *pipe, u32 *op) 
static int pp_mixer_setup(u32 disp_num,

		struct mdss_mdp_mixer *mixer)

{

	u32 flags, dspp_num, opmode = 0, lm_bitmask = 0;

	u32 flags, mixer_num, opmode = 0, lm_bitmask = 0;

	struct mdp_pgc_lut_data *pgc_config;

	struct pp_sts_type *pp_sts;

	struct mdss_mdp_ctl *ctl;
@@ -1382,21 +1384,32 @@ static int pp_mixer_setup(u32 disp_num, 


	if (!mixer || !mixer->ctl || !mdata)

		return -EINVAL;

	dspp_num = mixer->num;

	mixer_num = mixer->num;

	ctl = mixer->ctl;

	lm_bitmask = (BIT(6) << mixer_num);



	/* no corresponding dspp */

	if ((mixer->type != MDSS_MDP_MIXER_TYPE_INTF) ||

		(dspp_num >= mdata->nmixers_intf))

	/* Assign appropriate flags after mixer index validation */

	if (mixer->type == MDSS_MDP_MIXER_TYPE_INTF) {

		if (mixer_num >= mdata->nmixers_intf) {

			pr_err("bad intf mixer index = %d total = %d\n",

				mixer_num, mdata->nmixers_intf);

			return 0;

	if (disp_num < MDSS_BLOCK_DISP_NUM)

		flags = mdss_pp_res->pp_disp_flags[disp_num];

	else

		flags = 0;



	lm_bitmask = (dspp_num == MDSS_MDP_DSPP3) ?

		BIT(20) : (BIT(6) << dspp_num);

		}

		if (mixer_num == MDSS_MDP_DSPP3)

			lm_bitmask = BIT(20);

	} else if (mixer->type == MDSS_MDP_MIXER_TYPE_WRITEBACK) {

		if (mixer_num >= mdata->nmixers_wb +

				mdata->nmixers_intf) {

			pr_err("bad wb mixer index = %d total = %d\n",

				mixer_num,

				mdata->nmixers_intf + mdata->nmixers_wb);

			return 0;

		}

	} else {

		return 0;

	}



	flags = mdss_pp_res->pp_disp_flags[disp_num];

	pp_sts = &mdss_pp_res->pp_disp_sts[disp_num];

	/* GC_LUT is in layer mixer */

	if (flags & PP_FLAGS_DIRTY_ARGC) {
@@ -1416,7 +1429,7 @@ static int pp_mixer_setup(u32 disp_num, 


	/* update LM opmode if LM needs flush */

	if ((pp_sts->argc_sts & PP_STS_ENABLE) &&

		(ctl->flush_bits & lm_bitmask)) {

		(flags & PP_FLAGS_DIRTY_ARGC)) {

		addr = mixer->base + MDSS_MDP_REG_LM_OP_MODE;

		opmode = readl_relaxed(addr);

		opmode |= (1 << 0); /* GC_LUT_EN */
@@ -1781,6 +1794,7 @@ int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl) 
	u32 mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];

	u32 disp_num;

	int i, req = -1;

	bool wb_mixer = false;

	bool valid_mixers = true;

	bool valid_ad_panel = true;

	if ((!ctl->mfd) || (!mdss_pp_res) || (!mdata))
@@ -1788,15 +1802,25 @@ int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl) 


	/* treat fb_num the same as block logical id*/

	disp_num = ctl->mfd->index;

	if (disp_num >= MDSS_MAX_MIXER_DISP_NUM) {

		pr_warn("Invalid display number found, %u", disp_num);

		return -EINVAL;

	}



	mixer_cnt = mdss_mdp_get_ctl_mixers(disp_num, mixer_id);

	if (!mixer_cnt) {

		valid_mixers = false;

		/* Check if disp_num corresponds to writeback mixer */

		if (ctl->mixer_left &&

		   (ctl->mixer_left->type == MDSS_MDP_MIXER_TYPE_WRITEBACK)) {

			wb_mixer = true;

		} else {

			ret = -EINVAL;

		pr_warn("Configuring post processing without mixers, err = %d\n",

			pr_warn("No mixers for post processing err = %d\n",

				ret);

			goto exit;

		}

	}

	if (mdata->nad_cfgs == 0)

		valid_mixers = false;

	for (i = 0; i < mixer_cnt && valid_mixers; i++) {
@@ -1818,7 +1842,10 @@ int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl) 
	mutex_lock(&mdss_pp_mutex);



	flags = mdss_pp_res->pp_disp_flags[disp_num];

	if (!wb_mixer)

		pa_v2_flags = mdss_pp_res->pa_v2_disp_cfg[disp_num].flags;

	else

		pa_v2_flags = 0;



	/*

	 * If a LUT based PP feature needs to be reprogrammed during resume,
@@ -1844,7 +1871,7 @@ int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl) 
		pp_dspp_setup(disp_num, ctl->mixer_right);

	}

	/* clear dirty flag */

	if (disp_num < MDSS_BLOCK_DISP_NUM) {

	if (disp_num < MDSS_MAX_MIXER_DISP_NUM) {

		mdss_pp_res->pp_disp_flags[disp_num] = 0;

		if (disp_num < mdata->nad_cfgs)

			mdata->ad_cfgs[disp_num].reg_sts = 0;