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Commit c4cd8ec5 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: clock-gcc-8909: Add a new level of SVS for MDP"

parents b1938b21 084002de

drivers/clk/qcom/clock-gcc-8909.c

+42 −39
Original line number Diff line number Diff line
@@ -285,6 +285,7 @@ static void __iomem *virt_bases[N_BASES]; 


enum vdd_dig_levels {

	VDD_DIG_NONE,

	VDD_DIG_LOWER,

	VDD_DIG_LOW,

	VDD_DIG_NOMINAL,

	VDD_DIG_HIGH,
@@ -293,7 +294,8 @@ enum vdd_dig_levels { 


static int vdd_corner[] = {

	RPM_REGULATOR_CORNER_NONE,              /* VDD_DIG_NONE */

	RPM_REGULATOR_CORNER_SVS_KRAIT,         /* VDD_DIG_LOW SVS */

	RPM_REGULATOR_CORNER_SVS_KRAIT,         /* VDD_DIG_LOWER SVS */

	RPM_REGULATOR_CORNER_SVS_SOC,           /* VDD_DIG_LOW SVS */

	RPM_REGULATOR_CORNER_NORMAL,            /* VDD_DIG_NOMINAL */

	RPM_REGULATOR_CORNER_SUPER_TURBO,       /* VDD_DIG_HIGH */

};
@@ -477,7 +479,7 @@ static struct rcg_clk camss_top_ahb_clk_src = { 
	.c = {

		.dbg_name = "camss_top_ahb_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 40000000, NOMINAL, 80000000),

		VDD_DIG_FMAX_MAP2(LOWER, 40000000, NOMINAL, 80000000),

		CLK_INIT(camss_top_ahb_clk_src.c),

	},

};
@@ -497,7 +499,7 @@ static struct rcg_clk csi0_clk_src = { 
	.c = {

		.dbg_name = "csi0_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),

		CLK_INIT(csi0_clk_src.c),

	},

};
@@ -511,7 +513,7 @@ static struct rcg_clk csi1_clk_src = { 
	.c = {

		.dbg_name = "csi1_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),

		CLK_INIT(csi1_clk_src.c),

	},

};
@@ -538,7 +540,7 @@ static struct rcg_clk vfe0_clk_src = { 
	.c = {

		.dbg_name = "vfe0_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,

		VDD_DIG_FMAX_MAP3(LOWER, 133330000, NOMINAL, 266670000, HIGH,

					320000000),

		CLK_INIT(vfe0_clk_src.c),

	},
@@ -560,7 +562,7 @@ static struct rcg_clk vcodec0_clk_src = { 
	.c = {

		.dbg_name = "vcodec0_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,

		VDD_DIG_FMAX_MAP3(LOWER, 133330000, NOMINAL, 266670000, HIGH,

					307200000),

		CLK_INIT(vcodec0_clk_src.c),

	},
@@ -581,7 +583,7 @@ static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup1_i2c_apps_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP1(LOW, 50000000),

		VDD_DIG_FMAX_MAP1(LOWER, 50000000),

		CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),

	},

};
@@ -606,7 +608,7 @@ static struct rcg_clk blsp1_qup1_spi_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup1_spi_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),

		VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),

		CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),

	},

};
@@ -620,7 +622,7 @@ static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup2_i2c_apps_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP1(LOW, 50000000),

		VDD_DIG_FMAX_MAP1(LOWER, 50000000),

		CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),

	},

};
@@ -634,7 +636,7 @@ static struct rcg_clk blsp1_qup2_spi_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup2_spi_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),

		VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),

		CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),

	},

};
@@ -648,7 +650,7 @@ static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup3_i2c_apps_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP1(LOW, 50000000),

		VDD_DIG_FMAX_MAP1(LOWER, 50000000),

		CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),

	},

};
@@ -662,7 +664,7 @@ static struct rcg_clk blsp1_qup3_spi_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup3_spi_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),

		VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),

		CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),

	},

};
@@ -676,7 +678,7 @@ static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup4_i2c_apps_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP1(LOW, 50000000),

		VDD_DIG_FMAX_MAP1(LOWER, 50000000),

		CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),

	},

};
@@ -690,7 +692,7 @@ static struct rcg_clk blsp1_qup4_spi_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup4_spi_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),

		VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),

		CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),

	},

};
@@ -704,7 +706,7 @@ static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup5_i2c_apps_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP1(LOW, 50000000),

		VDD_DIG_FMAX_MAP1(LOWER, 50000000),

		CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),

	},

};
@@ -718,7 +720,7 @@ static struct rcg_clk blsp1_qup5_spi_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup5_spi_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),

		VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),

		CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),

	},

};
@@ -732,7 +734,7 @@ static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup6_i2c_apps_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP1(LOW, 50000000),

		VDD_DIG_FMAX_MAP1(LOWER, 50000000),

		CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),

	},

};
@@ -746,7 +748,7 @@ static struct rcg_clk blsp1_qup6_spi_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_qup6_spi_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),

		VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),

		CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),

	},

};
@@ -779,7 +781,7 @@ static struct rcg_clk blsp1_uart1_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_uart1_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000),

		VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),

		CLK_INIT(blsp1_uart1_apps_clk_src.c),

	},

};
@@ -793,7 +795,7 @@ static struct rcg_clk blsp1_uart2_apps_clk_src = { 
	.c = {

		.dbg_name = "blsp1_uart2_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000),

		VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),

		CLK_INIT(blsp1_uart2_apps_clk_src.c),

	},

};
@@ -813,7 +815,7 @@ static struct rcg_clk camss_gp0_clk_src = { 
	.c = {

		.dbg_name = "camss_gp0_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),

		CLK_INIT(camss_gp0_clk_src.c),

	},

};
@@ -827,7 +829,7 @@ static struct rcg_clk camss_gp1_clk_src = { 
	.c = {

		.dbg_name = "camss_gp1_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),

		CLK_INIT(camss_gp1_clk_src.c),

	},

};
@@ -847,7 +849,7 @@ static struct rcg_clk mclk0_clk_src = { 
	.c = {

		.dbg_name = "mclk0_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP1(LOW, 66670000),

		VDD_DIG_FMAX_MAP1(LOWER, 66670000),

		CLK_INIT(mclk0_clk_src.c),

	},

};
@@ -861,7 +863,7 @@ static struct rcg_clk mclk1_clk_src = { 
	.c = {

		.dbg_name = "mclk1_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP1(LOW, 66670000),

		VDD_DIG_FMAX_MAP1(LOWER, 66670000),

		CLK_INIT(mclk1_clk_src.c),

	},

};
@@ -881,7 +883,7 @@ static struct rcg_clk csi0phytimer_clk_src = { 
	.c = {

		.dbg_name = "csi0phytimer_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),

		CLK_INIT(csi0phytimer_clk_src.c),

	},

};
@@ -903,7 +905,7 @@ static struct rcg_clk crypto_clk_src = { 
	.c = {

		.dbg_name = "crypto_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP2(LOW, 80000000, NOMINAL, 160000000),

		VDD_DIG_FMAX_MAP2(LOWER, 80000000, NOMINAL, 160000000),

		CLK_INIT(crypto_clk_src.c),

	},

};
@@ -922,7 +924,7 @@ static struct rcg_clk gp1_clk_src = { 
	.c = {

		.dbg_name = "gp1_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),

		CLK_INIT(gp1_clk_src.c),

	},

};
@@ -936,7 +938,7 @@ static struct rcg_clk gp2_clk_src = { 
	.c = {

		.dbg_name = "gp2_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),

		CLK_INIT(gp2_clk_src.c),

	},

};
@@ -950,7 +952,7 @@ static struct rcg_clk gp3_clk_src = { 
	.c = {

		.dbg_name = "gp3_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),

		CLK_INIT(gp3_clk_src.c),

	},

};
@@ -968,7 +970,7 @@ static struct rcg_clk byte0_clk_src = { 
	.c = {

		.dbg_name = "byte0_clk_src",

		.ops = &clk_ops_byte,

		VDD_DIG_FMAX_MAP1(LOW, 125000000),

		VDD_DIG_FMAX_MAP1(LOWER, 125000000),

		CLK_INIT(byte0_clk_src.c),

	},

};
@@ -987,7 +989,7 @@ static struct rcg_clk esc0_clk_src = { 
	.c = {

		.dbg_name = "esc0_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP1(LOW, 19200000),

		VDD_DIG_FMAX_MAP1(LOWER, 19200000),

		CLK_INIT(esc0_clk_src.c),

	},

};
@@ -1013,7 +1015,8 @@ static struct rcg_clk mdp_clk_src = { 
	.c = {

		.dbg_name = "mdp_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP2(LOW, 160000000, NOMINAL, 307200000),

		VDD_DIG_FMAX_MAP3(LOWER, 160000000, LOW, 200000000, NOMINAL,

			      307200000),

		CLK_INIT(mdp_clk_src.c),

	},

};
@@ -1032,7 +1035,7 @@ static struct rcg_clk pclk0_clk_src = { 
	.c = {

		.dbg_name = "pclk0_clk_src",

		.ops = &clk_ops_pixel,

		VDD_DIG_FMAX_MAP1(LOW, 83333333.33),

		VDD_DIG_FMAX_MAP1(LOWER, 83333333.33),

		CLK_INIT(pclk0_clk_src.c),

	},

};
@@ -1051,7 +1054,7 @@ static struct rcg_clk vsync_clk_src = { 
	.c = {

		.dbg_name = "vsync_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP1(LOW, 19200000),

		VDD_DIG_FMAX_MAP1(LOWER, 19200000),

		CLK_INIT(vsync_clk_src.c),

	},

};
@@ -1079,7 +1082,7 @@ static struct rcg_clk gfx3d_clk_src = { 
	.c = {

		.dbg_name = "gfx3d_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP3(LOW, 200000000, NOMINAL, 307200000, HIGH,

		VDD_DIG_FMAX_MAP3(LOWER, 200000000, NOMINAL, 307200000, HIGH,

					409600000),

		CLK_INIT(gfx3d_clk_src.c),

	},
@@ -1099,7 +1102,7 @@ static struct rcg_clk pdm2_clk_src = { 
	.c = {

		.dbg_name = "pdm2_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP1(LOW, 64000000),

		VDD_DIG_FMAX_MAP1(LOWER, 64000000),

		CLK_INIT(pdm2_clk_src.c),

	},

};
@@ -1125,7 +1128,7 @@ static struct rcg_clk sdcc1_apps_clk_src = { 
	.c = {

		.dbg_name = "sdcc1_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 50000000, NOMINAL, 200000000),

		CLK_INIT(sdcc1_apps_clk_src.c),

	},

};
@@ -1139,7 +1142,7 @@ static struct rcg_clk sdcc2_apps_clk_src = { 
	.c = {

		.dbg_name = "sdcc2_apps_clk_src",

		.ops = &clk_ops_rcg_mnd,

		VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 200000000),

		VDD_DIG_FMAX_MAP2(LOWER, 50000000, NOMINAL, 200000000),

		CLK_INIT(sdcc2_apps_clk_src.c),

	},

};
@@ -1159,7 +1162,7 @@ static struct rcg_clk usb_hs_system_clk_src = { 
	.c = {

		.dbg_name = "usb_hs_system_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP2(LOW, 57142857.14, NOMINAL, 80000000),

		VDD_DIG_FMAX_MAP2(LOWER, 57142857.14, NOMINAL, 80000000),

		CLK_INIT(usb_hs_system_clk_src.c),

	},

};