Merge "xhci-plat: Don't enable legacy PCI interrupts." (c3cec45f) · Commits · e / devices / android_kernel_sony_msm8994

drivers/usb/host/xhci-plat.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -33,7 +33,7 @@ static void xhci_plat_quirks(struct device dev, struct xhci_hcd xhci)
		* here that the generic code does not try to make a pci_dev from our
		* dev struct in order to setup MSI
		*/
		xhci->quirks \|= XHCI_BROKEN_MSI;
		xhci->quirks \|= XHCI_PLAT;

		if (!pdata)
		return;

drivers/usb/host/xhci.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -332,9 +332,14 @@ static void xhci_cleanup_msix(struct xhci_hcd *xhci)
		static int xhci_try_enable_msi(struct usb_hcd *hcd)
		{
		struct xhci_hcd *xhci = hcd_to_xhci(hcd);
		struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
		struct pci_dev *pdev;
		int ret;

		/* The xhci platform device has set up IRQs through usb_add_hcd. */
		if (xhci->quirks & XHCI_PLAT)
		return 0;

		pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
		/*
		* Some Fresco Logic host controllers advertise MSI, but fail to
		* generate interrupts. Don't even try to enable MSI.

drivers/usb/host/xhci.h

+5 −4

Original line number	Diff line number	Diff line
		@@ -1519,6 +1519,7 @@ struct xhci_hcd {
		#define XHCI_SPURIOUS_REBOOT (1 << 13)
		#define XHCI_COMP_MODE_QUIRK (1 << 14)
		#define XHCI_AVOID_BEI (1 << 15)
		#define XHCI_PLAT (1 << 16)
		/*
		* In Synopsis DWC3 controller, PORTSC register access involves multiple clock
		* domains. When the software does a PORTSC write, handshakes are needed
		@@ -1533,7 +1534,7 @@ struct xhci_hcd {
		* The workaround is to give some delay (5 mac2_clk -> UTMI clock = 60 MHz ->
		* (16.66 ns x 5 = 84ns) ~100ns after writing to the PORTSC register.
		*/
		#define XHCI_PORTSC_DELAY (1 << 16)
		#define XHCI_PORTSC_DELAY (1 << 17)
		/*
		* In Synopsis DWC3 controller, XHCI RESET takes some time complete. If PIPE
		* RESET is not complete by the time USBCMD.RUN bit is set then HC fails to
		@@ -1541,7 +1542,7 @@ struct xhci_hcd {
		*
		* The workaround is to give worst case pipe delay ~350us after resetting HC
		*/
		#define XHCI_RESET_DELAY (1 << 17)
		#define XHCI_RESET_DELAY (1 << 18)
		/*
		* When the Endpoint State (EP State) is not Error/Stopped, a Set TR Dequeue
		* Pointer Command must generate a Command Completion Event with the Completion
		@@ -1550,8 +1551,8 @@ struct xhci_hcd {
		*
		* The workaround is to handle TRB Error and Context State Error in same way
		*/
		#define XHCI_TR_DEQ_ERR_QUIRK (1 << 18)
		#define XHCI_NO_SELECTIVE_SUSPEND (1 << 19)
		#define XHCI_TR_DEQ_ERR_QUIRK (1 << 19)
		#define XHCI_NO_SELECTIVE_SUSPEND (1 << 20)
		unsigned int num_active_eps;
		unsigned int limit_active_eps;
		/* There are two roothubs to keep track of bus suspend info for */