Loading Documentation/devicetree/bindings/ufs/ufs-msm.txt +4 −4 Original line number Diff line number Diff line Loading @@ -16,9 +16,9 @@ Required properties: - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply - clocks : List of phandle and clock specifier pairs - clock-names : List of clock input name strings sorted in the same order as the clocks property. "ref_clk_src", "ref_clk_parent", "ref_clk", "tx_iface_clk" & "rx_iface_clk" are mandatory order as the clocks property. "ref_clk_src", "ref_clk", "tx_iface_clk" & "rx_iface_clk" are mandatory but "ref_clk_parent" is optional Optional properties: - vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply Loading drivers/phy/phy-qcom-ufs.c +35 −14 Original line number Diff line number Diff line Loading @@ -142,8 +142,8 @@ out: return err; } int ufs_qcom_phy_clk_get(struct phy *phy, const char *name, struct clk **clk_out) static int __ufs_qcom_phy_clk_get(struct phy *phy, const char *name, struct clk **clk_out, bool err_print) { struct clk *clk; int err = 0; Loading @@ -153,6 +153,7 @@ int ufs_qcom_phy_clk_get(struct phy *phy, clk = devm_clk_get(dev, name); if (IS_ERR(clk)) { err = PTR_ERR(clk); if (err_print) dev_err(dev, "failed to get %s err %d", name, err); } else { *clk_out = clk; Loading @@ -161,6 +162,12 @@ int ufs_qcom_phy_clk_get(struct phy *phy, return err; } int ufs_qcom_phy_clk_get(struct phy *phy, const char *name, struct clk **clk_out) { return __ufs_qcom_phy_clk_get(phy, name, clk_out, true); } int ufs_qcom_phy_init_clks(struct phy *generic_phy, struct ufs_qcom_phy *phy_common) Loading @@ -182,10 +189,12 @@ ufs_qcom_phy_init_clks(struct phy *generic_phy, if (err) goto out; err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk_parent", &phy_common->ref_clk_parent); if (err) goto out; /* * "ref_clk_parent" is optional hence don't abort init if it's not * found. */ __ufs_qcom_phy_clk_get(generic_phy, "ref_clk_parent", &phy_common->ref_clk_parent, false); err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk", &phy_common->ref_clk); Loading Loading @@ -352,12 +361,18 @@ int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy) goto out; } /* * "ref_clk_parent" is optional clock hence make sure that clk reference * is available before trying to enable the clock. */ if (phy->ref_clk_parent) { ret = clk_prepare_enable(phy->ref_clk_parent); if (ret) { dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n", __func__, ret); goto out_disable_src; } } ret = clk_prepare_enable(phy->ref_clk); if (ret) { Loading @@ -370,6 +385,7 @@ int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy) goto out; out_disable_parent: if (phy->ref_clk_parent) clk_disable_unprepare(phy->ref_clk_parent); out_disable_src: clk_disable_unprepare(phy->ref_clk_src); Loading Loading @@ -407,6 +423,11 @@ void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy) if (phy->is_ref_clk_enabled) { clk_disable_unprepare(phy->ref_clk); /* * "ref_clk_parent" is optional clock hence make sure that clk * reference is available before trying to disable the clock. */ if (phy->ref_clk_parent) clk_disable_unprepare(phy->ref_clk_parent); clk_disable_unprepare(phy->ref_clk_src); phy->is_ref_clk_enabled = false; Loading Loading
Documentation/devicetree/bindings/ufs/ufs-msm.txt +4 −4 Original line number Diff line number Diff line Loading @@ -16,9 +16,9 @@ Required properties: - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply - clocks : List of phandle and clock specifier pairs - clock-names : List of clock input name strings sorted in the same order as the clocks property. "ref_clk_src", "ref_clk_parent", "ref_clk", "tx_iface_clk" & "rx_iface_clk" are mandatory order as the clocks property. "ref_clk_src", "ref_clk", "tx_iface_clk" & "rx_iface_clk" are mandatory but "ref_clk_parent" is optional Optional properties: - vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply Loading
drivers/phy/phy-qcom-ufs.c +35 −14 Original line number Diff line number Diff line Loading @@ -142,8 +142,8 @@ out: return err; } int ufs_qcom_phy_clk_get(struct phy *phy, const char *name, struct clk **clk_out) static int __ufs_qcom_phy_clk_get(struct phy *phy, const char *name, struct clk **clk_out, bool err_print) { struct clk *clk; int err = 0; Loading @@ -153,6 +153,7 @@ int ufs_qcom_phy_clk_get(struct phy *phy, clk = devm_clk_get(dev, name); if (IS_ERR(clk)) { err = PTR_ERR(clk); if (err_print) dev_err(dev, "failed to get %s err %d", name, err); } else { *clk_out = clk; Loading @@ -161,6 +162,12 @@ int ufs_qcom_phy_clk_get(struct phy *phy, return err; } int ufs_qcom_phy_clk_get(struct phy *phy, const char *name, struct clk **clk_out) { return __ufs_qcom_phy_clk_get(phy, name, clk_out, true); } int ufs_qcom_phy_init_clks(struct phy *generic_phy, struct ufs_qcom_phy *phy_common) Loading @@ -182,10 +189,12 @@ ufs_qcom_phy_init_clks(struct phy *generic_phy, if (err) goto out; err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk_parent", &phy_common->ref_clk_parent); if (err) goto out; /* * "ref_clk_parent" is optional hence don't abort init if it's not * found. */ __ufs_qcom_phy_clk_get(generic_phy, "ref_clk_parent", &phy_common->ref_clk_parent, false); err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk", &phy_common->ref_clk); Loading Loading @@ -352,12 +361,18 @@ int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy) goto out; } /* * "ref_clk_parent" is optional clock hence make sure that clk reference * is available before trying to enable the clock. */ if (phy->ref_clk_parent) { ret = clk_prepare_enable(phy->ref_clk_parent); if (ret) { dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n", __func__, ret); goto out_disable_src; } } ret = clk_prepare_enable(phy->ref_clk); if (ret) { Loading @@ -370,6 +385,7 @@ int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy) goto out; out_disable_parent: if (phy->ref_clk_parent) clk_disable_unprepare(phy->ref_clk_parent); out_disable_src: clk_disable_unprepare(phy->ref_clk_src); Loading Loading @@ -407,6 +423,11 @@ void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy) if (phy->is_ref_clk_enabled) { clk_disable_unprepare(phy->ref_clk); /* * "ref_clk_parent" is optional clock hence make sure that clk * reference is available before trying to disable the clock. */ if (phy->ref_clk_parent) clk_disable_unprepare(phy->ref_clk_parent); clk_disable_unprepare(phy->ref_clk_src); phy->is_ref_clk_enabled = false; Loading