Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c175ca9a authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add cayman CS check support 



Added to existing evergreen CS checker.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent e3487629

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ $(obj)/rs600.o: $(obj)/rs600_reg_safe.h 


$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h



$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h

$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h $(obj)/cayman_reg_safe.h



radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \

	radeon_irq.o r300_cmdbuf.o r600_cp.o

drivers/gpu/drm/radeon/evergreen_cs.c

+52 −3
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include "radeon.h"

#include "evergreend.h"

#include "evergreen_reg_safe.h"

#include "cayman_reg_safe.h"



static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,

					  struct radeon_cs_reloc **cs_reloc);
@@ -425,18 +426,28 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3 
{

	struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;

	struct radeon_cs_reloc *reloc;

	u32 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);

	u32 last_reg;

	u32 m, i, tmp, *ib;

	int r;



	if (p->rdev->family >= CHIP_CAYMAN)

		last_reg = ARRAY_SIZE(cayman_reg_safe_bm);

	else

		last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);



	i = (reg >> 7);

	if (i > last_reg) {

		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);

		return -EINVAL;

	}

	m = 1 << ((reg >> 2) & 31);

	if (p->rdev->family >= CHIP_CAYMAN) {

		if (!(cayman_reg_safe_bm[i] & m))

			return 0;

	} else {

		if (!(evergreen_reg_safe_bm[i] & m))

			return 0;

	}

	ib = p->ib->ptr;

	switch (reg) {

	/* force following reg to 0 in an attemp to disable out buffer
@@ -474,6 +485,20 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3 
	case DB_DEPTH_CONTROL:

		track->db_depth_control = radeon_get_ib_value(p, idx);

		break;

	case CAYMAN_DB_EQAA:

		if (p->rdev->family < CHIP_CAYMAN) {

			dev_warn(p->dev, "bad SET_CONTEXT_REG "

				 "0x%04X\n", reg);

			return -EINVAL;

		}

		break;

	case CAYMAN_DB_DEPTH_INFO:

		if (p->rdev->family < CHIP_CAYMAN) {

			dev_warn(p->dev, "bad SET_CONTEXT_REG "

				 "0x%04X\n", reg);

			return -EINVAL;

		}

		break;

	case DB_Z_INFO:

		r = evergreen_cs_packet_next_reloc(p, &reloc);

		if (r) {
@@ -559,9 +584,23 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3 
		track->cb_shader_mask = radeon_get_ib_value(p, idx);

		break;

	case PA_SC_AA_CONFIG:

		if (p->rdev->family >= CHIP_CAYMAN) {

			dev_warn(p->dev, "bad SET_CONTEXT_REG "

				 "0x%04X\n", reg);

			return -EINVAL;

		}

		tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;

		track->nsamples = 1 << tmp;

		break;

	case CAYMAN_PA_SC_AA_CONFIG:

		if (p->rdev->family < CHIP_CAYMAN) {

			dev_warn(p->dev, "bad SET_CONTEXT_REG "

				 "0x%04X\n", reg);

			return -EINVAL;

		}

		tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;

		track->nsamples = 1 << tmp;

		break;

	case CB_COLOR0_VIEW:

	case CB_COLOR1_VIEW:

	case CB_COLOR2_VIEW:
@@ -987,6 +1026,16 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 
			return -EINVAL;

		}

		break;

	case CAYMAN_PACKET3_DEALLOC_STATE:

		if (p->rdev->family < CHIP_CAYMAN) {

			DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");

			return -EINVAL;

		}

		if (pkt->count) {

			DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");

			return -EINVAL;

		}

		break;

	case PACKET3_INDEX_BASE:

		if (pkt->count != 1) {

			DRM_ERROR("bad INDEX_BASE\n");

drivers/gpu/drm/radeon/evergreend.h

+9 −0
Original line number Diff line number Diff line
@@ -1092,5 +1092,14 @@ 
#define SQ_TEX_RESOURCE_WORD6_0                         0x30018

#define SQ_TEX_RESOURCE_WORD7_0                         0x3001c



/* cayman 3D regs */

#define CAYMAN_VGT_OFFCHIP_LDS_BASE			0x89B0

#define CAYMAN_DB_EQAA					0x28804

#define CAYMAN_DB_DEPTH_INFO				0x2803C

#define CAYMAN_PA_SC_AA_CONFIG				0x28BE0

#define         CAYMAN_MSAA_NUM_SAMPLES_SHIFT           0

#define         CAYMAN_MSAA_NUM_SAMPLES_MASK            0x7

/* cayman packet3 addition */

#define	CAYMAN_PACKET3_DEALLOC_STATE			0x14



#endif