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Commit c041a436 authored by Eugene Yasman's avatar Eugene Yasman
Browse files

power: smb349-dual: Add SMB349 Dual Charger driver 



SMB349 Dual Charger is a single path switch-mode
battery charger based on SMB349 working in conjunction
with an external charger on the same path.
SMB349 HW to HW suspend signal is used to prevent
SMB349 from charging when external charging is used.

Change-Id: Ibc54e4af874d465c87b1f14f23d380a03c214e07
Signed-off-by: default avatarEugene Yasman <eyasman@codeaurora.org>
parent dc82df31

Documentation/devicetree/bindings/power/smb349-dual-charger.txt

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+52 −0
Original line number Diff line number Diff line 
SMB349 Dual Charger



SMB349 Dual Charger is a single-path battery charger working

in conjunction with an additional external charger to hand-off

for HVDCP/WiPower charging on the same path.



The SMB349 charger interface is via I2C bus.

SMB349 suspend HW to HW signal is used to prevent charging while

HVDCP/WiPower charging is activated.



Required Properties:

- compatible:			Must be "qcom,smb349-dual-charger".

- reg:				The device 7-bit I2C address.

- qcom,chg-stat-gpio		GPIO which indicates the charger presence

				by level, as well as special events by pulses

				of 10ms each 300ms until cleared.

- qcom,ext-psy-name		This is a string and it point to the external

				power supply name, SMB349 Dual Charger driver

				controls the hand-off to/from this external

				power supply



Optional Properties:



- qcom,fastchg-current-max-ma	Fast Charging current in mA. Supported range is

				from 1000mA to 4000mA.

- qcom,charging-disabled	This is a bool property which disables charging.



- qcom,bms-psy-name		This is a string and it points to the bms

				power supply name.

- qcom,iterm-ma			Specifies the termination current to indicate end-of-charge.

				Possible values in mA - 100, 200, 300, 400, 500, 600, 700.

- qcom,iterm-disabled		Disables the termination current feature. This is a bool

				property.

- qcom,float-voltage-mv	 	Float Voltage in mV - the maximum voltage up to which

				the battery is charged. Supported range 3460mV to 4720mV

- qcom,recharge-mv		Recharge threshold in mV - the offset from the float-volatge

				as which the charger restarts charging. Possible

				values are 50mV and 100mV.

- qcom,recharge-disabled	Boolean value which disables the auto-recharge.



Example:

	i2c@f9967000 {

		smb349-dual-charger@1b {

			compatible = "qcom,smb349-dual-charger";

			reg = <0x1b>;

			interrupt-parent = <&spmi_bus>;

			qcom,chg-stat-gpio = <&pm8994_gpios 6 0x1>;

			qcom,fastchg-current-max-ma = <2000>;

			qcom,battery-psy-name = "cradle-charger";

			qcom,ext-psy-name = "battery";

		};

	};

drivers/power/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -360,6 +360,16 @@ config SMB349_USB_CHARGER 
	 notification support. The driver controls SMB349 via I2C and

	 supports device-tree interface.



config SMB349_DUAL_CHARGER

	tristate "smb349 dual charger"

	depends on I2C

	help

	 Say Y to enable support for the SMB349 dual charger single path

	 switching mode charger. The driver supports charging in conjuction

	 with an external charger on the same path by providing hand-off

	 control and charge-current limiting. The driver controls SMB349

	 via I2C in STAT IRQ driven mode and supports device-tree interface.



config SMB350_CHARGER

	tristate "smb350 charger"

	depends on I2C

drivers/power/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o 
obj-$(CONFIG_CHARGER_BQ2415X)	+= bq2415x_charger.o

obj-$(CONFIG_POWER_AVS)		+= avs/

obj-$(CONFIG_SMB349_USB_CHARGER)   += smb349-charger.o

obj-$(CONFIG_SMB349_DUAL_CHARGER)   += smb349-dual-charger.o

obj-$(CONFIG_SMB350_CHARGER)   += smb350_charger.o

obj-$(CONFIG_SMB135X_CHARGER)   += smb135x-charger.o

obj-$(CONFIG_SMB1360_CHARGER_FG) += smb1360-charger-fg.o

drivers/power/smb349-charger.c

+2 −156
Original line number Diff line number Diff line 
/* Copyright (c) 2013 The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -26,141 +26,7 @@ 
#include <linux/of.h>

#include <linux/of_gpio.h>

#include <linux/mutex.h>



/* Config/Control registers */

#define CHG_CURRENT_CTRL_REG		0x0

#define CHG_OTH_CURRENT_CTRL_REG	0x1

#define VARIOUS_FUNC_REG		0x2

#define VFLOAT_REG			0x3

#define CHG_CTRL_REG			0x4

#define CHG_PIN_EN_CTRL_REG		0x6

#define THERM_A_CTRL_REG		0x7

#define FAULT_INT_REG			0xC

#define STATUS_INT_REG			0xD



/* Command registers */

#define CMD_A_REG			0x30

#define CMD_B_REG			0x31



/* Revision register */

#define CHG_REVISION_REG		0x34



/* IRQ status registers */

#define IRQ_A_REG			0x35

#define IRQ_B_REG			0x36

#define IRQ_C_REG			0x37

#define IRQ_D_REG			0x38

#define IRQ_E_REG			0x39

#define IRQ_F_REG			0x3A



/* Status registers */

#define STATUS_C_REG			0x3D

#define STATUS_D_REG			0x3E

#define STATUS_E_REG			0x3F



/* Config bits */

#define CMD_A_CHG_ENABLE_BIT			BIT(1)

#define CMD_A_VOLATILE_W_PERM_BIT		BIT(7)

#define CMD_A_CHG_SUSP_EN_BIT			BIT(2)

#define CMD_A_CHG_SUSP_EN_MASK			BIT(2)

#define CMD_A_OTG_ENABLE_BIT			BIT(4)

#define CMD_A_OTG_ENABLE_MASK			BIT(4)

#define CMD_B_CHG_HC_ENABLE_BIT			BIT(0)

#define CMD_B_CHG_USB3_ENABLE_BIT		BIT(2)

#define CMD_B_CHG_USB_500_900_ENABLE_BIT	BIT(1)

#define CHG_CTRL_AUTO_RECHARGE_ENABLE_BIT	0x0

#define CHG_CTRL_CURR_TERM_END_CHG_BIT		0x0

#define CHG_CTRL_BATT_MISSING_DET_THERM_IO	(BIT(5) | BIT(4))

#define CHG_CTRL_AUTO_RECHARGE_MASK		BIT(7)

#define CHG_CTRL_CURR_TERM_END_MASK		BIT(6)

#define CHG_CTRL_BATT_MISSING_DET_MASK		(BIT(5) | BIT(4))

#define CHG_CTRL_RECHG_100MV_BIT		BIT(3)

#define CHG_CTRL_RECHG_50_100_MASK		BIT(3)

#define CHG_OTH_CTRL_USB_2_3_REG_CTRL_BIT	0

#define CHG_OTH_CTRL_USB_2_3_PIN_REG_MASK	BIT(1)

#define CHG_ITERM_MASK				0x1C

#define CHG_PIN_CTRL_USBCS_REG_BIT		0x0

#define CHG_PIN_CTRL_CHG_EN_LOW_PIN_BIT		(BIT(5) | BIT(6))

#define CHG_PIN_CTRL_CHG_EN_LOW_REG_BIT		0x0

#define CHG_PIN_CTRL_CHG_EN_MASK		(BIT(5) | BIT(6))

#define CHG_PIN_CTRL_USBCS_REG_MASK		BIT(4)

#define CHG_PIN_CTRL_APSD_IRQ_BIT		BIT(1)

#define CHG_PIN_CTRL_APSD_IRQ_MASK		BIT(1)

#define CHG_PIN_CTRL_CHG_ERR_IRQ_BIT		BIT(2)

#define CHG_PIN_CTRL_CHG_ERR_IRQ_MASK		BIT(2)

#define VARIOUS_FUNC_USB_SUSP_EN_REG_BIT	BIT(7)

#define VARIOUS_FUNC_USB_SUSP_MASK		BIT(7)

#define VARIOUS_FUNC_APSD_EN_BIT		BIT(2)

#define VARIOUS_FUNC_APSD_MASK			BIT(2)

#define FAULT_INT_HOT_COLD_HARD_BIT		BIT(7)

#define FAULT_INT_HOT_COLD_SOFT_BIT		BIT(6)

#define FAULT_INT_INPUT_UV_BIT			BIT(2)

#define FAULT_INT_AICL_COMPLETE_BIT		BIT(1)

#define STATUS_INT_CHG_TIMEOUT_BIT		BIT(7)

#define STATUS_INT_OTG_DETECT_BIT		BIT(6)

#define STATUS_INT_BATT_OV_BIT			BIT(5)

#define STATUS_INT_TERM_TAPER_BIT		BIT(4)

#define STATUS_INT_FAST_CHG_BIT			BIT(3)

#define STATUS_INT_MISSING_BATT_BIT		BIT(1)

#define STATUS_INT_LOW_BATT_BIT			BIT(0)

#define THERM_A_THERM_MONITOR_EN_BIT		0x0

#define THERM_A_THERM_MONITOR_EN_MASK		BIT(4)

#define VFLOAT_MASK				0x3F

#define SMB349_REV_MASK				0x0F

#define SMB349_REV_A4				0x4



/* IRQ status bits */

#define IRQ_A_HOT_HARD_BIT			BIT(6)

#define IRQ_A_COLD_HARD_BIT			BIT(4)

#define IRQ_A_HOT_SOFT_BIT			BIT(2)

#define IRQ_A_COLD_SOFT_BIT			BIT(0)

#define IRQ_B_BATT_MISSING_BIT			BIT(4)

#define IRQ_B_BATT_LOW_BIT			BIT(2)

#define IRQ_B_BATT_OV_BIT			BIT(6)

#define IRQ_B_PRE_FAST_CHG_BIT			BIT(0)

#define IRQ_C_TAPER_CHG_BIT			BIT(2)

#define IRQ_C_TERM_BIT				BIT(0)

#define IRQ_C_INT_OVER_TEMP_BIT			BIT(6)

#define IRQ_D_CHG_TIMEOUT_BIT			(BIT(0) | BIT(2))

#define IRQ_D_AICL_DONE_BIT			BIT(4)

#define IRQ_D_APSD_COMPLETE			BIT(6)

#define IRQ_E_INPUT_UV_BIT			BIT(0)

#define IRQ_E_INPUT_OV_BIT			BIT(2)

#define IRQ_E_AFVC_ACTIVE                       BIT(4)

#define IRQ_F_OTG_VALID_BIT			BIT(2)

#define IRQ_F_OTG_BATT_FAIL_BIT			BIT(4)

#define IRQ_F_OTG_OC_BIT			BIT(6)

#define IRQ_F_POWER_OK				BIT(0)



/* Status  bits */

#define STATUS_C_CHARGING_MASK			(BIT(1) | BIT(2))

#define STATUS_C_FAST_CHARGING			BIT(2)

#define STATUS_C_PRE_CHARGING			BIT(1)

#define STATUS_C_TAPER_CHARGING			(BIT(2) | BIT(1))

#define STATUS_C_CHG_ERR_STATUS_BIT		BIT(6)

#define STATUS_C_CHG_ENABLE_STATUS_BIT		BIT(0)

#define STATUS_C_CHG_HOLD_OFF_BIT		BIT(3)

#define STATUS_D_PORT_OTHER			BIT(0)

#define STATUS_D_PORT_SDP			BIT(1)

#define STATUS_D_PORT_DCP			BIT(2)

#define STATUS_D_PORT_CDP			BIT(3)

#define STATUS_D_PORT_ACA_A			BIT(4)

#define STATUS_D_PORT_ACA_B			BIT(5)

#define STATUS_D_PORT_ACA_C			BIT(6)

#define STATUS_D_PORT_ACA_DOCK			BIT(7)



/* constants */

#define USB2_MIN_CURRENT_MA		100

#define USB2_MAX_CURRENT_MA		500

#define USB3_MAX_CURRENT_MA		900

#define AC_CHG_CURRENT_MASK		0x0F

#define SMB349_IRQ_REG_COUNT		6

#define SMB349_FAST_CHG_MIN_MA		1000

#define SMB349_FAST_CHG_STEP_MA		200

#define SMB349_FAST_CHG_MAX_MA		4000

#define SMB349_FAST_CHG_SHIFT		4

#define SMB_FAST_CHG_CURRENT_MASK	0xF0

#define SMB349_DEFAULT_BATT_CAPACITY	50

#include "smb349-charger.h"



enum {

	WRKARND_APSD_FAIL = BIT(0),
@@ -327,10 +193,6 @@ static int smb349_fastchg_current_set(struct smb349_charger *chip) 
				SMB_FAST_CHG_CURRENT_MASK, temp);

}



#define MIN_FLOAT_MV		3460

#define MAX_FLOAT_MV		4720

#define VFLOAT_STEP_MV		20



static int smb349_float_voltage_set(struct smb349_charger *chip, int vfloat_mv)

{

	u8 temp;
@@ -431,14 +293,6 @@ static int smb349_regulator_init(struct smb349_charger *chip) 
	return rc;

}



#define CHG_ITERM_100MA			0x18

#define CHG_ITERM_200MA			0x0

#define CHG_ITERM_300MA			0x04

#define CHG_ITERM_400MA			0x08

#define CHG_ITERM_500MA			0x0C

#define CHG_ITERM_600MA			0x10

#define CHG_ITERM_700MA			0x14



static int smb349_hw_init(struct smb349_charger *chip)

{

	int rc;
@@ -1201,9 +1055,6 @@ static struct irq_handler_info handlers[] = { 
	},

};



#define IRQ_LATCHED_MASK	0x02

#define IRQ_STATUS_MASK		0x01

#define BITS_PER_IRQ		2

static irqreturn_t smb349_chg_stat_handler(int irq, void *dev_id)

{

	struct smb349_charger *chip = dev_id;
@@ -1333,7 +1184,6 @@ static void smb349_external_power_changed(struct power_supply *psy) 
	power_supply_changed(&chip->batt_psy);

}



#define LAST_CNFG_REG	0x13

static int show_cnfg_regs(struct seq_file *m, void *data)

{

	struct smb349_charger *chip = m->private;
@@ -1365,8 +1215,6 @@ static const struct file_operations cnfg_debugfs_ops = { 
	.release	= single_release,

};



#define FIRST_CMD_REG	0x30

#define LAST_CMD_REG	0x33

static int show_cmd_regs(struct seq_file *m, void *data)

{

	struct smb349_charger *chip = m->private;
@@ -1398,8 +1246,6 @@ static const struct file_operations cmd_debugfs_ops = { 
	.release	= single_release,

};



#define FIRST_STATUS_REG	0x35

#define LAST_STATUS_REG		0x3F

static int show_status_regs(struct seq_file *m, void *data)

{

	struct smb349_charger *chip = m->private;

drivers/power/smb349-charger.h

0 → 100644
+176 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef SMB349_CHARGER_H

#define SMB349_CHARGER_H



/* Config/Control registers */

#define CHG_CURRENT_CTRL_REG		0x0

#define CHG_OTH_CURRENT_CTRL_REG	0x1

#define VARIOUS_FUNC_REG		0x2

#define VFLOAT_REG			0x3

#define CHG_CTRL_REG			0x4

#define CHG_PIN_EN_CTRL_REG		0x6

#define THERM_A_CTRL_REG		0x7

#define OTG_TLIM_THERM_CTRL_REG		0xA

#define HARD_SOFT_TLIM_CTRL_REG		0xB

#define FAULT_INT_REG			0xC

#define STATUS_INT_REG			0xD



/* Command registers */

#define CMD_A_REG			0x30

#define CMD_B_REG			0x31



/* Revision register */

#define CHG_REVISION_REG		0x34



/* IRQ status registers */

#define IRQ_A_REG			0x35

#define IRQ_B_REG			0x36

#define IRQ_C_REG			0x37

#define IRQ_D_REG			0x38

#define IRQ_E_REG			0x39

#define IRQ_F_REG			0x3A



/* Status registers */

#define STATUS_C_REG			0x3D

#define STATUS_D_REG			0x3E

#define STATUS_E_REG			0x3F



/* Config bits */

#define CMD_A_CHG_ENABLE_BIT			BIT(1)

#define CMD_A_VOLATILE_W_PERM_BIT		BIT(7)

#define CMD_A_CHG_SUSP_EN_BIT			BIT(2)

#define CMD_A_CHG_SUSP_EN_MASK			BIT(2)

#define CMD_A_OTG_ENABLE_BIT			BIT(4)

#define CMD_A_OTG_ENABLE_MASK			BIT(4)

#define CMD_B_CHG_HC_ENABLE_BIT			BIT(0)

#define CMD_B_CHG_USB3_ENABLE_BIT		BIT(2)

#define CMD_B_CHG_USB_500_900_ENABLE_BIT	BIT(1)

#define CHG_CTRL_AUTO_RECHARGE_ENABLE_BIT	0x0

#define CHG_CTRL_CURR_TERM_END_CHG_BIT		0x0

#define CHG_CTRL_BATT_MISSING_DET_THERM_IO	(BIT(5) | BIT(4))

#define CHG_CTRL_AUTO_RECHARGE_MASK		BIT(7)

#define CHG_CTRL_CURR_TERM_END_MASK		BIT(6)

#define CHG_CTRL_BATT_MISSING_DET_MASK		(BIT(5) | BIT(4))

#define CHG_CTRL_RECHG_100MV_BIT		BIT(3)

#define CHG_CTRL_RECHG_50_100_MASK		BIT(3)

#define CHG_OTH_CTRL_USB_2_3_REG_CTRL_BIT	0

#define CHG_OTH_CTRL_USB_2_3_PIN_REG_MASK	BIT(1)

#define CHG_ITERM_MASK				0x1C

#define CHG_PIN_CTRL_USBCS_REG_BIT		0x0

#define CHG_PIN_CTRL_CHG_EN_LOW_PIN_BIT		(BIT(5) | BIT(6))

#define CHG_PIN_CTRL_CHG_EN_LOW_REG_BIT		0x0

#define CHG_PIN_CTRL_CHG_EN_MASK		(BIT(5) | BIT(6))

#define CHG_PIN_CTRL_USBCS_REG_MASK		BIT(4)

#define CHG_PIN_CTRL_APSD_IRQ_BIT		BIT(1)

#define CHG_PIN_CTRL_APSD_IRQ_MASK		BIT(1)

#define CHG_PIN_CTRL_CHG_ERR_IRQ_BIT		BIT(2)

#define CHG_PIN_CTRL_CHG_ERR_IRQ_MASK		BIT(2)

#define VARIOUS_FUNC_USB_SUSP_EN_REG_BIT	BIT(7)

#define VARIOUS_FUNC_USB_SUSP_MASK		BIT(7)

#define VARIOUS_FUNC_APSD_EN_BIT		BIT(2)

#define VARIOUS_FUNC_APSD_MASK			BIT(2)

#define FAULT_INT_HOT_COLD_HARD_BIT		BIT(7)

#define FAULT_INT_HOT_COLD_SOFT_BIT		BIT(6)

#define FAULT_INT_INPUT_UV_BIT			BIT(2)

#define FAULT_INT_AICL_COMPLETE_BIT		BIT(1)

#define STATUS_INT_CHG_TIMEOUT_BIT		BIT(7)

#define STATUS_INT_OTG_DETECT_BIT		BIT(6)

#define STATUS_INT_BATT_OV_BIT			BIT(5)

#define STATUS_INT_TERM_TAPER_BIT		BIT(4)

#define STATUS_INT_FAST_CHG_BIT			BIT(3)

#define STATUS_INT_MISSING_BATT_BIT		BIT(1)

#define STATUS_INT_LOW_BATT_BIT			BIT(0)

#define THERM_A_THERM_MONITOR_EN_BIT		0x0

#define THERM_A_THERM_MONITOR_EN_MASK		BIT(4)

#define VFLOAT_MASK				0x3F

#define SMB349_REV_MASK				0x0F

#define SMB349_REV_A4				0x4



/* IRQ status bits */

#define IRQ_A_HOT_HARD_BIT			BIT(6)

#define IRQ_A_COLD_HARD_BIT			BIT(4)

#define IRQ_A_HOT_SOFT_BIT			BIT(2)

#define IRQ_A_COLD_SOFT_BIT			BIT(0)

#define IRQ_B_BATT_MISSING_BIT			BIT(4)

#define IRQ_B_BATT_LOW_BIT			BIT(2)

#define IRQ_B_BATT_OV_BIT			BIT(6)

#define IRQ_B_PRE_FAST_CHG_BIT			BIT(0)

#define IRQ_C_TAPER_CHG_BIT			BIT(2)

#define IRQ_C_TERM_BIT				BIT(0)

#define IRQ_C_INT_OVER_TEMP_BIT			BIT(6)

#define IRQ_D_CHG_TIMEOUT_BIT			(BIT(0) | BIT(2))

#define IRQ_D_AICL_DONE_BIT			BIT(4)

#define IRQ_D_APSD_COMPLETE			BIT(6)

#define IRQ_E_INPUT_UV_BIT			BIT(0)

#define IRQ_E_INPUT_OV_BIT			BIT(2)

#define IRQ_E_AFVC_ACTIVE                       BIT(4)

#define IRQ_F_OTG_VALID_BIT			BIT(2)

#define IRQ_F_OTG_BATT_FAIL_BIT			BIT(4)

#define IRQ_F_OTG_OC_BIT			BIT(6)

#define IRQ_F_POWER_OK				BIT(0)



/* Status  bits */

#define STATUS_C_CHARGING_MASK			(BIT(1) | BIT(2))

#define STATUS_C_FAST_CHARGING			BIT(2)

#define STATUS_C_PRE_CHARGING			BIT(1)

#define STATUS_C_TAPER_CHARGING			(BIT(2) | BIT(1))

#define STATUS_C_CHG_ERR_STATUS_BIT		BIT(6)

#define STATUS_C_CHG_ENABLE_STATUS_BIT		BIT(0)

#define STATUS_C_CHG_HOLD_OFF_BIT		BIT(3)

#define STATUS_D_PORT_OTHER			BIT(0)

#define STATUS_D_PORT_SDP			BIT(1)

#define STATUS_D_PORT_DCP			BIT(2)

#define STATUS_D_PORT_CDP			BIT(3)

#define STATUS_D_PORT_ACA_A			BIT(4)

#define STATUS_D_PORT_ACA_B			BIT(5)

#define STATUS_D_PORT_ACA_C			BIT(6)

#define STATUS_D_PORT_ACA_DOCK			BIT(7)



/* Constants */

#define USB2_MIN_CURRENT_MA		100

#define USB2_MAX_CURRENT_MA		500

#define USB3_MAX_CURRENT_MA		900

#define AC_CHG_CURRENT_MASK		0x0F

#define SMB349_IRQ_REG_COUNT		6

#define SMB349_FAST_CHG_MIN_MA		1000

#define SMB349_FAST_CHG_STEP_MA		200

#define SMB349_FAST_CHG_MAX_MA		4000

#define SMB349_FAST_CHG_SHIFT		4

#define SMB_FAST_CHG_CURRENT_MASK	0xF0

#define SMB349_DEFAULT_BATT_CAPACITY	50



#define MIN_FLOAT_MV		3460

#define MAX_FLOAT_MV		4720

#define VFLOAT_STEP_MV		20



/* Termination currents */

#define CHG_ITERM_100MA			0x18

#define CHG_ITERM_200MA			0x0

#define CHG_ITERM_300MA			0x04

#define CHG_ITERM_400MA			0x08

#define CHG_ITERM_500MA			0x0C

#define CHG_ITERM_600MA			0x10

#define CHG_ITERM_700MA			0x14



#define IRQ_LATCHED_MASK	0x02

#define IRQ_STATUS_MASK		0x01

#define BITS_PER_IRQ		2



#define LAST_CNFG_REG		0x13

#define FIRST_CMD_REG		0x30

#define LAST_CMD_REG		0x33

#define FIRST_STATUS_REG	0x35

#define LAST_STATUS_REG		0x3F



#endif /* SMB349_CHARGER_H */