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Commit c0177800 authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
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ARM: 6379/1: Assume new page cache pages have dirty D-cache 



There are places in Linux where writes to newly allocated page cache
pages happen without a subsequent call to flush_dcache_page() (several
PIO drivers including USB HCD). This patch changes the meaning of
PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
mapped page in update_mmu_cache().

The patch also sets the PG_arch_1 bit in the DMA cache maintenance
function to avoid additional cache flushing in update_mmu_cache().

Tested-by: default avatarRabin Vincent <rabin.vincent@stericsson.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 0fc73099

arch/arm/include/asm/cacheflush.h

+3 −3
Original line number Diff line number Diff line
@@ -137,10 +137,10 @@ 
#endif



/*

 * This flag is used to indicate that the page pointed to by a pte

 * is dirty and requires cleaning before returning it to the user.

 * This flag is used to indicate that the page pointed to by a pte is clean

 * and does not require cleaning before returning it to the user.

 */

#define PG_dcache_dirty PG_arch_1

#define PG_dcache_clean PG_arch_1



/*

 *	MM Cache Management

arch/arm/include/asm/tlbflush.h

+1 −1
Original line number Diff line number Diff line
@@ -560,7 +560,7 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); 
#endif



/*

 * if PG_dcache_dirty is set for the page, we need to ensure that any

 * If PG_dcache_clean is not set for the page, we need to ensure that any

 * cache entries for the kernels virtual memory range are written

 * back to the page.

 */

arch/arm/mm/copypage-v4mc.c

+1 −1
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from, 
{

	void *kto = kmap_atomic(to, KM_USER1);



	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))

	if (!test_and_set_bit(PG_dcache_clean, &from->flags))

		__flush_dcache_page(page_mapping(from), from);



	spin_lock(&minicache_lock);

arch/arm/mm/copypage-v6.c

+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to, 
	unsigned int offset = CACHE_COLOUR(vaddr);

	unsigned long kfrom, kto;



	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))

	if (!test_and_set_bit(PG_dcache_clean, &from->flags))

		__flush_dcache_page(page_mapping(from), from);



	/* FIXME: not highmem safe */

arch/arm/mm/copypage-xscale.c

+1 −1
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from, 
{

	void *kto = kmap_atomic(to, KM_USER1);



	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))

	if (!test_and_set_bit(PG_dcache_clean, &from->flags))

		__flush_dcache_page(page_mapping(from), from);



	spin_lock(&minicache_lock);