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Commit bf4f42b4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (27 commits)
  drm/radeon/kms: remove rv100 bios connector quirk
  drm/radeon/kms/pm: fix power state indexing on igp chips in dynpm mode
  DRM / radeon / KMS: Fix hibernation regression related to radeon PM (was: Re: [Regression, post-2.6.34] Hibernation broken on machines with radeon/KMS and r300)
  drm/radeon/kms/igp: fix possible divide by 0 in bandwidth code (v2)
  drm/radeon: add quirk to make HP nx6125 laptop resume.
  drm/radeon/kms: add some missing regs to evergreen gpu init
  drm/radeon/kms: fix typos in evergreen command checker
  drm/radeon/kms: avoid oops on mac r4xx cards
  fb: fix colliding defines for fb flags.
  drm/radeon/kms: Force HDP_NONSURF to maximum size
  drm/radeon/kms: disable frac fb dividers for rs6xx
  drm/radeon/kms: don't read attempt to read bios from VRAM on unposted GPU.
  drm/radeon/kms: fix typo in evergreen_gpu_init
  drm/radeon/kms: return ret in cursor_set failure path
  drm/ttm: non pooled page allocation should have GFP_USER set
  drm/radeon/r100/r200: fix calculation of compressed cube maps
  drm/radeon/r200: handle more hw tex coord types
  drm/radeon/kms: CS checker texture fixes for r1xx/r2xx/r3xx
  drm/radeon: add fake RN50 table for powerpc
  drm/fb: Fix video= mode computation
  ...
parents 1e31b0ff 2f9c6b0a

drivers/char/agp/generic.c

+2 −4
Original line number Diff line number Diff line
@@ -97,20 +97,18 @@ EXPORT_SYMBOL(agp_flush_chipset); 
void agp_alloc_page_array(size_t size, struct agp_memory *mem)

{

	mem->pages = NULL;

	mem->vmalloc_flag = false;



	if (size <= 2*PAGE_SIZE)

		mem->pages = kmalloc(size, GFP_KERNEL | __GFP_NORETRY);

		mem->pages = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);

	if (mem->pages == NULL) {

		mem->pages = vmalloc(size);

		mem->vmalloc_flag = true;

	}

}

EXPORT_SYMBOL(agp_alloc_page_array);



void agp_free_page_array(struct agp_memory *mem)

{

	if (mem->vmalloc_flag) {

	if (is_vmalloc_addr(mem->pages)) {

		vfree(mem->pages);

	} else {

		kfree(mem->pages);

drivers/gpu/drm/drm_fb_helper.c

+13 −6
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_fb_helper_conn 
				cvt = 1;

			break;

		case 'R':

			if (!cvt)

			if (cvt)

				rb = 1;

			break;

		case 'm':
@@ -1024,11 +1024,18 @@ static struct drm_display_mode *drm_pick_cmdline_mode(struct drm_fb_helper_conne 
	}



create_mode:

	mode = drm_cvt_mode(fb_helper_conn->connector->dev, cmdline_mode->xres,

			    cmdline_mode->yres,

	if (cmdline_mode->cvt)

		mode = drm_cvt_mode(fb_helper_conn->connector->dev,

				    cmdline_mode->xres, cmdline_mode->yres,

				    cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60,

				    cmdline_mode->rb, cmdline_mode->interlace,

				    cmdline_mode->margins);

	else

		mode = drm_gtf_mode(fb_helper_conn->connector->dev,

				    cmdline_mode->xres, cmdline_mode->yres,

				    cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60,

				    cmdline_mode->interlace,

				    cmdline_mode->margins);

	drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);

	list_add(&mode->head, &fb_helper_conn->connector->modes);

	return mode;

drivers/gpu/drm/radeon/atombios_crtc.c

+1 −1
Original line number Diff line number Diff line
@@ -498,7 +498,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
		if ((rdev->family == CHIP_RS600) ||

		    (rdev->family == CHIP_RS690) ||

		    (rdev->family == CHIP_RS740))

			pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |

			pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/

				       RADEON_PLL_PREFER_CLOSEST_LOWER);



		if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)	/* range limits??? */

drivers/gpu/drm/radeon/evergreen.c

+29 −6
Original line number Diff line number Diff line
@@ -607,7 +607,7 @@ static void evergreen_mc_program(struct radeon_device *rdev) 
	WREG32(MC_VM_FB_LOCATION, tmp);

	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));

	WREG32(HDP_NONSURFACE_INFO, (2 << 7));

	WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);

	WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

	if (rdev->flags & RADEON_IS_AGP) {

		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);

		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
@@ -1222,11 +1222,11 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
		ps_thread_count = 128;



	sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);

	sq_thread_resource_mgmt |= NUM_VS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;

	sq_thread_resource_mgmt |= NUM_GS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;

	sq_thread_resource_mgmt |= NUM_ES_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;

	sq_thread_resource_mgmt_2 = NUM_HS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;

	sq_thread_resource_mgmt_2 |= NUM_LS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;

	sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

	sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

	sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

	sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);

	sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);



	sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);

	sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
@@ -1260,6 +1260,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	WREG32(VGT_GS_VERTEX_REUSE, 16);

	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);



	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);

	WREG32(VGT_OUT_DEALLOC_CNTL, 16);



	WREG32(CB_PERF_CTR0_SEL_0, 0);

	WREG32(CB_PERF_CTR0_SEL_1, 0);

	WREG32(CB_PERF_CTR1_SEL_0, 0);
@@ -1269,6 +1272,26 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	WREG32(CB_PERF_CTR3_SEL_0, 0);

	WREG32(CB_PERF_CTR3_SEL_1, 0);



	/* clear render buffer base addresses */

	WREG32(CB_COLOR0_BASE, 0);

	WREG32(CB_COLOR1_BASE, 0);

	WREG32(CB_COLOR2_BASE, 0);

	WREG32(CB_COLOR3_BASE, 0);

	WREG32(CB_COLOR4_BASE, 0);

	WREG32(CB_COLOR5_BASE, 0);

	WREG32(CB_COLOR6_BASE, 0);

	WREG32(CB_COLOR7_BASE, 0);

	WREG32(CB_COLOR8_BASE, 0);

	WREG32(CB_COLOR9_BASE, 0);

	WREG32(CB_COLOR10_BASE, 0);

	WREG32(CB_COLOR11_BASE, 0);



	/* set the shader const cache sizes to 0 */

	for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)

		WREG32(i, 0);

	for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)

		WREG32(i, 0);



	hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);

	WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);

drivers/gpu/drm/radeon/evergreen_cs.c

+2 −2
Original line number Diff line number Diff line
@@ -1197,7 +1197,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 
					DRM_ERROR("bad SET_RESOURCE (tex)\n");

					return -EINVAL;

				}

				ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

				ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

				if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)

					ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);

				else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
@@ -1209,7 +1209,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 
					DRM_ERROR("bad SET_RESOURCE (tex)\n");

					return -EINVAL;

				}

				ib[idx+1+(i*8)+4] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

				ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

				mipmap = reloc->robj;

				r = evergreen_check_texture_resource(p,  idx+1+(i*8),

						texture, mipmap);