Loading arch/arm/boot/dts/qcom/msmzirc-sim.dts +4 −0 Original line number Diff line number Diff line Loading @@ -57,3 +57,7 @@ &qnand_1 { status = "ok"; }; &qrng { status = "ok"; }; arch/arm/boot/dts/qcom/msmzirc.dtsi +14 −0 Original line number Diff line number Diff line Loading @@ -1314,6 +1314,20 @@ }; }; qrng: rng@0x22000 { compatible = "qcom,msm-rng"; reg = <0x22000 0x140>; qcom,msm-rng-iface-clk; qcom,msm-bus,name = "msm-rng-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 618 0 0>, <1 618 0 800>; clocks = <&clock_gcc clk_gcc_prng_ahb_clk>; clock-names = "iface_clk"; }; qcom,qcedev@720000 { compatible = "qcom,qcedev"; reg = <0x720000 0x20000>, Loading Loading
arch/arm/boot/dts/qcom/msmzirc-sim.dts +4 −0 Original line number Diff line number Diff line Loading @@ -57,3 +57,7 @@ &qnand_1 { status = "ok"; }; &qrng { status = "ok"; };
arch/arm/boot/dts/qcom/msmzirc.dtsi +14 −0 Original line number Diff line number Diff line Loading @@ -1314,6 +1314,20 @@ }; }; qrng: rng@0x22000 { compatible = "qcom,msm-rng"; reg = <0x22000 0x140>; qcom,msm-rng-iface-clk; qcom,msm-bus,name = "msm-rng-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 618 0 0>, <1 618 0 800>; clocks = <&clock_gcc clk_gcc_prng_ahb_clk>; clock-names = "iface_clk"; }; qcom,qcedev@720000 { compatible = "qcom,qcedev"; reg = <0x720000 0x20000>, Loading