Merge "arm64: topology: Implement basic CPU topology support" (bd68e831) · Commits · e / devices / android_kernel_sony_msm8994

arch/arm64/Kconfig

+16 −0

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		@@ -211,6 +211,22 @@ config SMP

		If you don't know what to do here, say N.

		config SCHED_MC
		bool "Multi-core scheduler support"
		depends on SMP
		help
		Multi-core scheduler support improves the CPU scheduler's decision
		making when dealing with multi-core CPU chips at a cost of slightly
		increased overhead in some places. If unsure say N here.

		config SCHED_SMT
		bool "SMT scheduler support"
		depends on SMP
		help
		Improves the CPU scheduler's decision making when dealing with
		MultiThreading at a cost of slightly increased overhead in some
		places. If unsure say N here.

		config NR_CPUS
		int "Maximum number of CPUs (2-32)"
		range 2 32

arch/arm64/include/asm/topology.h

0 → 100644

+39 −0

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		#ifndef __ASM_TOPOLOGY_H
		#define __ASM_TOPOLOGY_H

		#ifdef CONFIG_SMP

		#include <linux/cpumask.h>

		struct cpu_topology {
		int thread_id;
		int core_id;
		int cluster_id;
		cpumask_t thread_sibling;
		cpumask_t core_sibling;
		};

		extern struct cpu_topology cpu_topology[NR_CPUS];

		#define topology_physical_package_id(cpu) (cpu_topology[cpu].cluster_id)
		#define topology_core_id(cpu) (cpu_topology[cpu].core_id)
		#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling)
		#define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling)

		#define mc_capable() (cpu_topology[0].cluster_id != -1)
		#define smt_capable() (cpu_topology[0].thread_id != -1)

		void init_cpu_topology(void);
		void store_cpu_topology(unsigned int cpuid);
		const struct cpumask *cpu_coregroup_mask(int cpu);

		#else

		static inline void init_cpu_topology(void) { }
		static inline void store_cpu_topology(unsigned int cpuid) { }

		#endif

		#include <asm-generic/topology.h>

		#endif /* _ASM_ARM_TOPOLOGY_H */

arch/arm64/kernel/Makefile

+1 −1

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		@@ -14,7 +14,7 @@ arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \
		arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
		sys_compat.o
		arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o
		arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o
		arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o
		arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_debug.o \
		perf_trace_counters.o
		arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o

arch/arm64/kernel/smp.c

+11 −0

Original line number	Diff line number	Diff line
		@@ -116,6 +116,11 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
		return ret;
		}

		static void smp_store_cpu_info(unsigned int cpuid)
		{
		store_cpu_topology(cpuid);
		}

		/*
		* This is the secondary CPU boot entry. We're using this CPUs
		* idle thread stack, but a set of temporary page tables.
		@@ -154,6 +159,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
		*/
		notify_cpu_starting(cpu);

		smp_store_cpu_info(cpu);

		/*
		* OK, now it's safe to let the boot CPU continue. Wait for
		* the CPU migration code to notice that the CPU is online
		@@ -401,6 +408,10 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
		int err;
		unsigned int cpu, ncores = num_possible_cpus();

		init_cpu_topology();

		smp_store_cpu_info(smp_processor_id());

		/*
		* are we trying to boot more cores than exist?
		*/

arch/arm64/kernel/topology.c

0 → 100644

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Original line number	Diff line number	Diff line
		/*
		* arch/arm64/kernel/topology.c
		*
		* Copyright (C) 2011,2013,2014 Linaro Limited.
		*
		* Based on the arm32 version written by Vincent Guittot in turn based on
		* arch/sh/kernel/topology.c
		*
		* This file is subject to the terms and conditions of the GNU General Public
		* License. See the file "COPYING" in the main directory of this archive
		* for more details.
		*/

		#include <linux/cpu.h>
		#include <linux/cpumask.h>
		#include <linux/init.h>
		#include <linux/percpu.h>
		#include <linux/node.h>
		#include <linux/nodemask.h>
		#include <linux/sched.h>

		#include <asm/topology.h>

		/*
		* cpu topology table
		*/
		struct cpu_topology cpu_topology[NR_CPUS];
		EXPORT_SYMBOL_GPL(cpu_topology);

		const struct cpumask *cpu_coregroup_mask(int cpu)
		{
		return &cpu_topology[cpu].core_sibling;
		}

		static void update_siblings_masks(unsigned int cpuid)
		{
		struct cpu_topology cpu_topo, cpuid_topo = &cpu_topology[cpuid];
		int cpu;

		if (cpuid_topo->cluster_id == -1) {
		/*
		* DT does not contain topology information for this cpu
		* reset it to default behaviour
		*/
		pr_debug("CPU%u: No topology information configured\n", cpuid);
		cpuid_topo->core_id = 0;
		cpumask_set_cpu(cpuid, &cpuid_topo->core_sibling);
		cpumask_set_cpu(cpuid, &cpuid_topo->thread_sibling);
		return;
		}

		/* update core and thread sibling masks */
		for_each_possible_cpu(cpu) {
		cpu_topo = &cpu_topology[cpu];

		if (cpuid_topo->cluster_id != cpu_topo->cluster_id)
		continue;

		cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
		if (cpu != cpuid)
		cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);

		if (cpuid_topo->core_id != cpu_topo->core_id)
		continue;

		cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
		if (cpu != cpuid)
		cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
		}
		}

		void store_cpu_topology(unsigned int cpuid)
		{
		update_siblings_masks(cpuid);
		}

		/*
		* init_cpu_topology is called at boot when only one cpu is running
		* which prevent simultaneous write access to cpu_topology array
		*/
		void __init init_cpu_topology(void)
		{
		unsigned int cpu;

		/* init core mask and power*/
		for_each_possible_cpu(cpu) {
		struct cpu_topology *cpu_topo = &cpu_topology[cpu];

		cpu_topo->thread_id = -1;
		cpu_topo->core_id = -1;
		cpu_topo->cluster_id = -1;
		cpumask_clear(&cpu_topo->core_sibling);
		cpumask_clear(&cpu_topo->thread_sibling);
		}
		}