Loading arch/arm/mach-msm/acpuclock-8226.c +5 −5 Original line number Diff line number Diff line Loading @@ -63,7 +63,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p1[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 0, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading @@ -74,7 +74,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p2[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading @@ -85,7 +85,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p4[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading @@ -99,7 +99,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p5[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading @@ -114,7 +114,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p6[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading Loading
arch/arm/mach-msm/acpuclock-8226.c +5 −5 Original line number Diff line number Diff line Loading @@ -63,7 +63,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p1[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 0, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading @@ -74,7 +74,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p2[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading @@ -85,7 +85,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p4[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading @@ -99,7 +99,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p5[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading @@ -114,7 +114,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p6[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, Loading