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Commit bb588820 authored by Christopher Staite's avatar Christopher Staite Committed by Alex Deucher
Browse files

drm/radeon: fix MC blackout on evergreen+ 



Force the crtc mem requests on/off immediately rather
than waiting for the double buffered updates to kick in.
Seems we miss the update in certain conditions.  Also
handle the DCE6 case.

Signed-off-by: default avatarChristopher Staite <chris@yourdreamnet.co.uk>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 48367432

drivers/gpu/drm/radeon/evergreen.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -1313,14 +1313,18 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav 
				if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {

				if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {

					radeon_wait_for_vblank(rdev, i);

					radeon_wait_for_vblank(rdev, i);

					tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;

					tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;

					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

					WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

					WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

				}

				}

			} else {

			} else {

				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

				if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {

				if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {

					radeon_wait_for_vblank(rdev, i);

					radeon_wait_for_vblank(rdev, i);

					tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;

					tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;

					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

					WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

					WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

				}

				}

			}

			}

			/* wait for the next frame */

			/* wait for the next frame */
@@ -1378,11 +1382,15 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s 
			if (ASIC_IS_DCE6(rdev)) {

			if (ASIC_IS_DCE6(rdev)) {

				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);

				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);

				tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;

				tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;

				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

				WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

				WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			} else {

			} else {

				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

				tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;

				tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;

				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

				WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

				WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			}

			}

			/* wait for the next frame */

			/* wait for the next frame */

			frame_count = radeon_get_vblank_counter(rdev, i);

			frame_count = radeon_get_vblank_counter(rdev, i);