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Commit bb24c471 authored by Jacob Pan's avatar Jacob Pan Committed by H. Peter Anvin
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x86, apbt: Moorestown APB system timer driver 



Moorestown platform does not have PIT or HPET platform timers.  Instead it
has a bank of eight APB timers.  The number of available timers to the os
is exposed via SFI mtmr tables.  All APB timer interrupts are routed via
ioapic rtes and delivered as MSI.
Currently, we use timer 0 and 1 for per cpu clockevent devices, timer 2
for clocksource.

Signed-off-by: default avatarJacob Pan <jacob.jun.pan@intel.com>
LKML-Reference: <43F901BD926A4E43B106BF17856F0755A318D2D2@orsmsx508.amr.corp.intel.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent cf089455

Documentation/kernel-parameters.txt

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@@ -2793,6 +2793,12 @@ and is between 256 and 4096 characters. It is defined in the file 
			default x2apic cluster mode on platforms

			supporting x2apic.



	x86_mrst_timer= [X86-32,APBT]

			Choose timer option for x86 Moorestown MID platform.

			Two valid options are apbt timer only and lapic timer

			plus one apbt timer for broadcast timer.

			x86_mrst_timer=apbt_only | lapic_and_apbt



	xd=		[HW,XT] Original XT pre-IDE (RLL encoded) disks.

	xd_geo=		See header of drivers/block/xd.c.

arch/x86/Kconfig

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@@ -390,6 +390,7 @@ config X86_MRST 
       bool "Moorestown MID platform"

	depends on X86_32

	depends on X86_EXTENDED_PLATFORM

	select APB_TIMER

	---help---

	  Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin

	  Internet Device(MID) platform. Moorestown consists of two chips:
@@ -612,6 +613,16 @@ config HPET_EMULATE_RTC 
	def_bool y

	depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y)



config APB_TIMER

       def_bool y if MRST

       prompt "Langwell APB Timer Support" if X86_MRST

       help

         APB timer is the replacement for 8254, HPET on X86 MID platforms.

         The APBT provides a stable time base on SMP

         systems, unlike the TSC, but it is more expensive to access,

         as it is off-chip. APB timers are always running regardless of CPU

         C states, they are used as per CPU clockevent device when possible.



# Mark as embedded because too many people got it wrong.

# The code disables itself when not needed.

config DMI

arch/x86/include/asm/apb_timer.h

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/*

 * apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare

 *

 * (C) Copyright 2009 Intel Corporation

 * Author: Jacob Pan (jacob.jun.pan@intel.com)

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * as published by the Free Software Foundation; version 2

 * of the License.

 *

 * Note:

 */



#ifndef ASM_X86_APBT_H

#define ASM_X86_APBT_H

#include <linux/sfi.h>



#ifdef CONFIG_APB_TIMER



/* Langwell DW APB timer registers */

#define APBTMR_N_LOAD_COUNT    0x00

#define APBTMR_N_CURRENT_VALUE 0x04

#define APBTMR_N_CONTROL       0x08

#define APBTMR_N_EOI           0x0c

#define APBTMR_N_INT_STATUS    0x10



#define APBTMRS_INT_STATUS     0xa0

#define APBTMRS_EOI            0xa4

#define APBTMRS_RAW_INT_STATUS 0xa8

#define APBTMRS_COMP_VERSION   0xac

#define APBTMRS_REG_SIZE       0x14



/* register bits */

#define APBTMR_CONTROL_ENABLE  (1<<0)

#define APBTMR_CONTROL_MODE_PERIODIC   (1<<1) /*1: periodic 0:free running */

#define APBTMR_CONTROL_INT     (1<<2)



/* default memory mapped register base */

#define LNW_SCU_ADDR           0xFF100000

#define LNW_EXT_TIMER_OFFSET   0x1B800

#define APBT_DEFAULT_BASE      (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET)

#define LNW_EXT_TIMER_PGOFFSET         0x800



/* APBT clock speed range from PCLK to fabric base, 25-100MHz */

#define APBT_MAX_FREQ          50

#define APBT_MIN_FREQ          1

#define APBT_MMAP_SIZE         1024



#define APBT_DEV_USED  1



extern void apbt_time_init(void);

extern struct clock_event_device *global_clock_event;

extern unsigned long apbt_quick_calibrate(void);

extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);

extern void apbt_setup_secondary_clock(void);

extern unsigned int boot_cpu_id;

extern int disable_apbt_percpu;



extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);

extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);

extern int sfi_mtimer_num;



#else /* CONFIG_APB_TIMER */



static inline unsigned long apbt_quick_calibrate(void) {return 0; }

static inline void apbt_time_init(void) {return 0; }



#endif

#endif /* ASM_X86_APBT_H */

arch/x86/kernel/Makefile

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@@ -87,6 +87,7 @@ obj-$(CONFIG_VM86) += vm86_32.o 
obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o



obj-$(CONFIG_HPET_TIMER) 	+= hpet.o

obj-$(CONFIG_APB_TIMER)		+= apb_timer.o



obj-$(CONFIG_K8_NB)		+= k8.o

obj-$(CONFIG_DEBUG_RODATA_TEST)	+= test_rodata.o

arch/x86/kernel/apb_timer.c

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