Loading arch/arm/boot/dts/qcom/mpq8092.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -1061,7 +1061,7 @@ reg-names = "maple_csr_base"; vdd-supply = <&gdsc_vpu>; clock-names = "core_clk", "iface_clk", "bus_clk", "vdp_clk", "vdp_bus_clk", "sleep_clk"; "vdp_bus_clk", "sleep_clk", "maple_bus_clk"; qcom,firmware-name = "vpu"; }; Loading arch/arm/mach-msm/clock-8092.c +2 −0 Original line number Diff line number Diff line Loading @@ -6891,6 +6891,8 @@ static struct clk_lookup mpq_clocks_8092[] = { CLK_LOOKUP("vdp_bus_clk", vpu_bus_clk.c, "fde0b000.qcom,pil-vpu"), CLK_LOOKUP("core_clk", vpu_maple_clk.c, "fde0b000.qcom,pil-vpu"), CLK_LOOKUP("sleep_clk", vpu_sleep_clk.c, "fde0b000.qcom,pil-vpu"), CLK_LOOKUP("maple_bus_clk", gcc_mmss_a5ss_axi_clk.c, "fde0b000.qcom,pil-vpu"), CLK_LOOKUP("iface_clk", vpu_ahb_clk.c, "fde0b000.qcom,vpu"), CLK_LOOKUP("bus_clk", vpu_axi_clk.c, "fde0b000.qcom,vpu"), Loading Loading
arch/arm/boot/dts/qcom/mpq8092.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -1061,7 +1061,7 @@ reg-names = "maple_csr_base"; vdd-supply = <&gdsc_vpu>; clock-names = "core_clk", "iface_clk", "bus_clk", "vdp_clk", "vdp_bus_clk", "sleep_clk"; "vdp_bus_clk", "sleep_clk", "maple_bus_clk"; qcom,firmware-name = "vpu"; }; Loading
arch/arm/mach-msm/clock-8092.c +2 −0 Original line number Diff line number Diff line Loading @@ -6891,6 +6891,8 @@ static struct clk_lookup mpq_clocks_8092[] = { CLK_LOOKUP("vdp_bus_clk", vpu_bus_clk.c, "fde0b000.qcom,pil-vpu"), CLK_LOOKUP("core_clk", vpu_maple_clk.c, "fde0b000.qcom,pil-vpu"), CLK_LOOKUP("sleep_clk", vpu_sleep_clk.c, "fde0b000.qcom,pil-vpu"), CLK_LOOKUP("maple_bus_clk", gcc_mmss_a5ss_axi_clk.c, "fde0b000.qcom,pil-vpu"), CLK_LOOKUP("iface_clk", vpu_ahb_clk.c, "fde0b000.qcom,vpu"), CLK_LOOKUP("bus_clk", vpu_axi_clk.c, "fde0b000.qcom,vpu"), Loading