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Commit ba52f174 authored by Xiaocheng Li's avatar Xiaocheng Li
Browse files

ARM: dts: msm: Add cpu clock controller nodes for MSM8939 



Add application clock controller device nodes for all cpus.

Change-Id: I7ff77178218a4a920cea51718f2992c8c15bfc26
Signed-off-by: default avatarXiaocheng Li <lix@codeaurora.org>
parent 673f6d76

arch/arm/boot/dts/qcom/msm8939.dtsi

+56 −0
Original line number Diff line number Diff line
@@ -43,48 +43,64 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc0>;

		};



		cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc1>;

		};



		cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc2>;

		};



		cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc3>;

		};



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc4>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc5>;

		};



		cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x2>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc6>;

		};



		cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			enable-method = "qcom,arm-cortex-acc";

			qcom,acc = <&acc7>;

		};

	};
@@ -171,6 +187,46 @@ 
		qcom,direct-connect-irqs = <29>;

	};



	acc0:clock-controller@b088000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b088000 0x1000>;

	};



	acc1:clock-controller@b098000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b098000 0x1000>;

	};



	acc2:clock-controller@b0a8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0a8000 0x1000>;

	};



	acc3:clock-controller@b0b8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b0b8000 0x1000>;

	};



	acc4:clock-controller@b188000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b188000 0x1000>;

	};



	acc5:clock-controller@b198000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b198000 0x1000>;

	};



	acc6:clock-controller@b1a8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b1a8000 0x1000>;

	};



	acc7:clock-controller@b1b8000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0x0b1b8000 0x1000>;

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <1 2 0xf08>,