Merge "msm: kgsl: Clean up OCMEM/GMEM" (b8d2a788) · Commits · e / devices / android_kernel_sony_msm8994

drivers/gpu/msm/adreno-gpulist.h

+8 −1

Original line number	Diff line number	Diff line
		@@ -21,10 +21,11 @@
		* @major: Match for the major version of the GPU
		* @minor: Match for the minor version of the GPU
		* @patchid: Match for the patch revision of the GPU
		* @features: Common adreno features supported by this core
		* @pm4fw: Filename for th PM4 firmware
		* @pfpfw: Filename for the PFP firmware
		* @gpudev: Pointer to the GPU family specific functions for this core
		* @gmem_size: Size of GMEM (or OCMEM) for the core
		* @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core
		* @sync_lock_pm4_ver: For IOMMUv0 cores the version of PM4 microcode that
		* supports the sync lock mechanism
		* @sync_lock_pfp_ver: For IOMMUv0 cores the version of PFP microcode that
		@@ -40,6 +41,7 @@
		static const struct adreno_gpulist {
		enum adreno_gpurev gpurev;
		unsigned int core, major, minor, patchid;
		unsigned long features;
		const char *pm4fw;
		const char *pfpfw;
		struct adreno_gpudev *gpudev;
		@@ -86,6 +88,7 @@ static const struct adreno_gpulist {
		.major = 3,
		.minor = 0,
		.patchid = ANY_ID,
		.features = ADRENO_USES_OCMEM,
		.pm4fw = "a330_pm4.fw",
		.pfpfw = "a330_pfp.fw",
		.gpudev = &adreno_a3xx_gpudev,
		@@ -109,6 +112,7 @@ static const struct adreno_gpulist {
		.patchid = 0x10,
		.pm4fw = "a330_pm4.fw",
		.pfpfw = "a330_pfp.fw",
		.features = ADRENO_USES_OCMEM,
		.gpudev = &adreno_a3xx_gpudev,
		.gmem_size = SZ_128K,
		.sync_lock_pm4_ver = NO_VER,
		@@ -125,6 +129,7 @@ static const struct adreno_gpulist {
		.major = 0,
		.minor = 5,
		.patchid = 0x12,
		.features = ADRENO_USES_OCMEM,
		.pm4fw = "a330_pm4.fw",
		.pfpfw = "a330_pfp.fw",
		.gpudev = &adreno_a3xx_gpudev,
		@@ -169,6 +174,7 @@ static const struct adreno_gpulist {
		.major = 1,
		.minor = 0,
		.patchid = 0x10,
		.features = ADRENO_USES_OCMEM,
		.pm4fw = "a330_pm4.fw",
		.pfpfw = "a330_pfp.fw",
		.gpudev = &adreno_a3xx_gpudev,
		@@ -186,6 +192,7 @@ static const struct adreno_gpulist {
		.major = 2,
		.minor = 0,
		.patchid = ANY_ID,
		.features = ADRENO_USES_OCMEM,
		.pm4fw = "a420_pm4.fw",
		.pfpfw = "a420_pfp.fw",
		.gpudev = &adreno_a4xx_gpudev,

drivers/gpu/msm/adreno.c

+12 −20

Original line number	Diff line number	Diff line
		@@ -96,7 +96,6 @@ static struct adreno_device device_3d0 = {
		.mem_log = KGSL_LOG_LEVEL_DEFAULT,
		.pwr_log = KGSL_LOG_LEVEL_DEFAULT,
		},
		.gmem_base = 0,
		.gmem_size = SZ_256K,
		.pfp_fw = NULL,
		.pm4_fw = NULL,
		@@ -1269,6 +1268,7 @@ adreno_identify_gpu(struct adreno_device *adreno_dev)
		adreno_dev->pfp_jt_addr = adreno_gpulist[i].pfp_jt_addr;
		adreno_dev->pfp_bstrp_size = adreno_gpulist[i].pfp_bstrp_size;
		adreno_dev->pfp_bstrp_ver = adreno_gpulist[i].pfp_bstrp_ver;
		adreno_dev->features = adreno_gpulist[i].features;
		adreno_dev->gpulist_index = i;
		/*
		* Initialize uninitialzed gpu registers, only needs to be done once
		@@ -1552,12 +1552,9 @@ err:

		#ifdef CONFIG_MSM_OCMEM
		static int
		adreno_ocmem_gmem_malloc(struct adreno_device *adreno_dev)
		adreno_ocmem_malloc(struct adreno_device *adreno_dev)
		{
		if (!(adreno_is_a330(adreno_dev) \|\|
		adreno_is_a305b(adreno_dev) \|\|
		adreno_is_a310(adreno_dev) \|\|
		adreno_is_a4xx(adreno_dev)))
		if (!adreno_dev->features & ADRENO_USES_OCMEM)
		return 0;

		if (adreno_dev->ocmem_hdl == NULL) {
		@@ -1569,14 +1566,14 @@ adreno_ocmem_gmem_malloc(struct adreno_device *adreno_dev)
		}

		adreno_dev->gmem_size = adreno_dev->ocmem_hdl->len;
		adreno_dev->ocmem_base = adreno_dev->ocmem_hdl->addr;
		adreno_dev->gmem_base = adreno_dev->ocmem_hdl->addr;
		}

		return 0;
		}

		static void
		adreno_ocmem_gmem_free(struct adreno_device *adreno_dev)
		adreno_ocmem_free(struct adreno_device *adreno_dev)
		{
		if (adreno_dev->ocmem_hdl != NULL) {
		ocmem_free(OCMEM_GRAPHICS, adreno_dev->ocmem_hdl);
		@@ -1585,13 +1582,13 @@ adreno_ocmem_gmem_free(struct adreno_device *adreno_dev)
		}
		#else
		static int
		adreno_ocmem_gmem_malloc(struct adreno_device *adreno_dev)
		adreno_ocmem_malloc(struct adreno_device *adreno_dev)
		{
		return 0;
		}

		static void
		adreno_ocmem_gmem_free(struct adreno_device *adreno_dev)
		adreno_ocmem_free(struct adreno_device *adreno_dev)
		{
		}
		#endif
		@@ -1826,7 +1823,7 @@ static int _adreno_start(struct adreno_device *adreno_dev)
		if (status)
		goto error_clk_off;

		status = adreno_ocmem_gmem_malloc(adreno_dev);
		status = adreno_ocmem_malloc(adreno_dev);
		if (status) {
		KGSL_DRV_ERR(device, "OCMEM malloc failed\n");
		goto error_mmu_off;
		@@ -1973,7 +1970,7 @@ static int adreno_stop(struct kgsl_device *device)
		kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF);
		del_timer_sync(&device->idle_timer);

		adreno_ocmem_gmem_free(adreno_dev);
		adreno_ocmem_free(adreno_dev);

		/* Save active coresight registers if applicable */
		adreno_coresight_stop(adreno_dev);
		@@ -2794,14 +2791,9 @@ int adreno_idle(struct kgsl_device *device)

		BUG_ON(!mutex_is_locked(&device->mutex));

		if (adreno_is_a3xx(adreno_dev) \|\| adreno_is_a4xx(adreno_dev))
		kgsl_cffdump_regpoll(device,
		adreno_getreg(adreno_dev, ADRENO_REG_RBBM_STATUS) << 2,
		0x00000000, 0x80000000);
		else
		kgsl_cffdump_regpoll(device,
		adreno_getreg(adreno_dev, ADRENO_REG_RBBM_STATUS) << 2,
		0x110, 0x110);

		while (time_before(jiffies, wait)) {
		/*

drivers/gpu/msm/adreno.h

+4 −3

Original line number	Diff line number	Diff line
		@@ -36,6 +36,9 @@
		#define ADRENO_CHIPID_MINOR(_id) (((_id) >> 8) & 0xFF)
		#define ADRENO_CHIPID_PATCH(_id) ((_id) & 0xFF)

		/* Adreno core features */
		#define ADRENO_USES_OCMEM BIT(0)

		/* Flags to control command packet settings */
		#define KGSL_CMD_FLAGS_NONE 0
		#define KGSL_CMD_FLAGS_PMODE BIT(0)
		@@ -159,6 +162,7 @@ struct adreno_device {
		unsigned int pm4_fw_version;
		struct adreno_ringbuffer ringbuffer;
		struct adreno_gpudev *gpudev;
		unsigned long features;
		unsigned int wait_timeout;
		unsigned int pm4_jt_idx;
		unsigned int pm4_jt_addr;
		@@ -176,7 +180,6 @@ struct adreno_device {
		unsigned int ft_pf_policy;
		unsigned int gpulist_index;
		struct ocmem_buf *ocmem_hdl;
		unsigned int ocmem_base;
		struct adreno_profile profile;
		struct adreno_dispatcher dispatcher;
		struct kgsl_memdesc pwron_fixup;
		@@ -491,8 +494,6 @@ struct adreno_gpudev {
		* so define them in the structure and use them as variables.
		*/
		const struct adreno_reg_offsets *reg_offsets;
		/* keeps track of when we need to execute the draw workaround code */
		int ctx_switches_since_last_draw;

		struct adreno_perfcounters *perfcounters;
		const struct adreno_invalid_countables

drivers/gpu/msm/adreno_a3xx.c

+3 −5

Original line number	Diff line number	Diff line
		@@ -2094,12 +2094,10 @@ static void a3xx_start(struct adreno_device *adreno_dev)
		kgsl_regwrite(device, A3XX_RBBM_GPR0_CTL,
		A310_RBBM_GPR0_CTL_DEFAULT);

		/* Set the OCMEM base address for A330 */
		if (adreno_is_a330(adreno_dev) \|\|
		adreno_is_a305b(adreno_dev) \|\| adreno_is_a310(adreno_dev)) {
		if (adreno_dev->features & ADRENO_USES_OCMEM)
		kgsl_regwrite(device, A3XX_RB_GMEM_BASE_ADDR,
		(unsigned int)(adreno_dev->ocmem_base >> 14));
		}
		(unsigned int)(adreno_dev->gmem_base >> 14));

		/* Turn on protection */
		a3xx_protect_init(device);

drivers/gpu/msm/adreno_a4xx.c

+3 −3

Original line number	Diff line number	Diff line
		/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -383,9 +383,9 @@ static void a4xx_start(struct adreno_device *adreno_dev)
		kgsl_regwrite(device, A4XX_RBBM_INTERFACE_HANG_INT_CTL,
		(1 << 30) \| 0xFFFF);

		/* Set the OCMEM base address for A4XX */
		/* Set the GMEM/OCMEM base address for A4XX */
		kgsl_regwrite(device, A4XX_RB_GMEM_BASE_ADDR,
		(unsigned int)(adreno_dev->ocmem_base >> 14));
		(unsigned int)(adreno_dev->gmem_base >> 14));

		/* Turn on performance counters */
		kgsl_regwrite(device, A4XX_RBBM_PERFCTR_CTL, 0x01);