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Commit b726e3a4 authored by Shrenuj Bansal's avatar Shrenuj Bansal Committed by Jordan Crouse
Browse files

msm: kgsl: Remove A4XX references from ringbuffer_submitcmd()



adreno_ringbuffer_submitcmd() is a neutral function and should not
use specific GPU family registers and functions. Replace all A4XX
references with generic adreno functions and registers.

Change-Id: Ifc2b2ceaaeb5f3e05d20efb43f542b858225b829
Signed-off-by: default avatarShrenuj Bansal <shrenujb@codeaurora.org>
parent 3bc1fc8b
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+2 −0
Original line number Diff line number Diff line
@@ -402,6 +402,7 @@ enum adreno_regs {
	ADRENO_REG_UCHE_INVALIDATE0,
	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO,
	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,
	ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,
	ADRENO_REG_REGISTER_MAX,
};

@@ -576,6 +577,7 @@ struct adreno_gpudev {
		unsigned int counter, unsigned int countable);
	uint64_t (*perfcounter_read)(struct adreno_device *adreno_dev,
		unsigned int group, unsigned int counter);
	uint64_t (*alwayson_counter_read)(struct adreno_device *adreno_dev);
	bool (*is_sptp_idle)(struct adreno_device *);
	void (*enable_pc)(struct adreno_device *);
	void (*enable_ppd)(struct adreno_device *);
+3 −0
Original line number Diff line number Diff line
@@ -932,6 +932,8 @@ static unsigned int a4xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
				A4XX_RBBM_PERFCTR_LOAD_VALUE_LO),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,
				A4XX_RBBM_PERFCTR_LOAD_VALUE_HI),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONTROL,
				A4XX_RBBM_SECVID_TRUST_CONTROL),
};

const struct adreno_reg_offsets a4xx_reg_offsets = {
@@ -1570,6 +1572,7 @@ struct adreno_gpudev adreno_a4xx_gpudev = {
	.start = a4xx_start,
	.perfcounter_enable = a3xx_perfcounter_enable,
	.perfcounter_read = a3xx_perfcounter_read,
	.alwayson_counter_read = a4xx_alwayson_counter_read,
	.snapshot = a4xx_snapshot,
	.is_sptp_idle = a4xx_is_sptp_idle,
	.enable_pc = a4xx_enable_pc,
+2 −2
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@
#include "adreno_ringbuffer.h"

#include "a3xx_reg.h"
#include "adreno_a4xx.h"

#define GSL_RB_NOP_SIZEDWORDS				2

@@ -1252,6 +1251,7 @@ int adreno_ringbuffer_submitcmd(struct adreno_device *adreno_dev,
		struct kgsl_cmdbatch *cmdbatch)
{
	struct kgsl_device *device = &adreno_dev->dev;
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
	struct kgsl_memobj_node *ib;
	unsigned int numibs = 0;
	unsigned int *link;
@@ -1429,7 +1429,7 @@ int adreno_ringbuffer_submitcmd(struct adreno_device *adreno_dev,
		profile_buffer->wall_clock_s = ts.tv_sec;
		profile_buffer->wall_clock_ns = ts.tv_nsec;
		profile_buffer->gpu_ticks_queued =
			a4xx_alwayson_counter_read(adreno_dev);
			gpudev->alwayson_counter_read(adreno_dev);
	}

	ret = adreno_ringbuffer_addcmds(rb, flags,