msm: kgsl: Set CGC_HLSQ_TP_EARLY_CYC to 2 to prevent timing issue for A4XX

CGC_HLSQ_TP_EARLY_CYC should be set to 2 or greater to prevent a
timing issue with HLSQ_TP_CLK_EN in A4XX. This setting ensures that
the internal HLSQ clock is able to synchronize with rest of the
GPU core.

CRs-fixed: 554357
Change-Id: Ib15560dc98a249dc3e77add4728b48a944cfc48d
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>