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Commit b642c641 authored by Shubhraprakash Das's avatar Shubhraprakash Das
Browse files

msm: kgsl: Set CGC_HLSQ_TP_EARLY_CYC to 2 to prevent timing issue for A4XX 



CGC_HLSQ_TP_EARLY_CYC should be set to 2 or greater to prevent a
timing issue with HLSQ_TP_CLK_EN in A4XX. This setting ensures that
the internal HLSQ clock is able to synchronize with rest of the
GPU core.

CRs-fixed: 554357
Change-Id: Ib15560dc98a249dc3e77add4728b48a944cfc48d
Signed-off-by: default avatarShubhraprakash Das <sadas@codeaurora.org>
parent c255ffa1

drivers/gpu/msm/a4xx_reg.h

+5 −0
Original line number Diff line number Diff line
@@ -120,6 +120,11 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_RBBM_CFG_DEBBUS_PTRC0		0x65

#define A4XX_RBBM_CFG_DEBBUS_PTRC1		0x66

#define A4XX_RBBM_CFG_DEBBUS_LOADREG		0x67



#define A4XX_RBBM_CLOCK_DELAY_HLSQ		0x8c

#define A4XX_CGC_HLSQ_TP_EARLY_CYC_MASK		0x00700000

#define A4XX_CGC_HLSQ_TP_EARLY_CYC_SHIFT	20



#define A4XX_RBBM_CFG_DEBBUS_IDX		0x93

#define A4XX_RBBM_CFG_DEBBUS_CLRC		0x94

#define A4XX_RBBM_CFG_DEBBUS_LOADIVT		0x95

drivers/gpu/msm/adreno_a4xx.c

+11 −0
Original line number Diff line number Diff line
@@ -305,6 +305,17 @@ static void a4xx_start(struct adreno_device *adreno_dev) 
	/* On A420 cores turn on SKIP_IB2_DISABLE in addition to the default */

	kgsl_regwrite(device, A4XX_CP_DEBUG, A4XX_CP_DEBUG_DEFAULT |

			(adreno_is_a420(adreno_dev) ? (1 << 29) : 0));

	/*

	 * For A420 set RBBM_CLOCK_DELAY_HLSQ.CGC_HLSQ_TP_EARLY_CYC >= 2

	 * due to timing issue with HLSQ_TP_CLK_EN

	 */

	if (adreno_is_a420(adreno_dev)) {

		unsigned int val;

		kgsl_regread(device, A4XX_RBBM_CLOCK_DELAY_HLSQ, &val);

		val &= ~A4XX_CGC_HLSQ_TP_EARLY_CYC_MASK;

		val |= 2 << A4XX_CGC_HLSQ_TP_EARLY_CYC_SHIFT;

		kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_HLSQ, val);

	}

}



int a4xx_perfcounter_enable_vbif(struct kgsl_device *device,