Merge "ARM: dts: msm: Add DT entries for SATA controller and PHY on APQ8084"

		status = "disabled";

	};

	sataphy0: sataphy@0xfc581000 {

		compatible = "qcom,sataphy";

		reg = <0xfc581000 0x400>, <0xfd4ab20c 0x4>;

		reg-names = "phy_mem", "phy_sel";

		#phy-cells = <0>;

		vdda-phy-supply = <&pma8084_l4>;

		vdda-pll-supply = <&pma8084_l12>;

		vdda-phy-max-microamp = <50000>;

		vdda-pll-max-microamp = <1000>;

		status = "disabled";

	};

	sata0: sata@0xfc580000 {

		compatible = "qcom,msm-ahci";

		reg = <0xfc580000 0x400>;

		interrupts = <0 31 0>;

		phys = <&sataphy0>;

		phy-names = "sata-6g";

		clock-names = "core_clk", "iface_clk", "pmalive_clk",

				"rxoob_clk", "asic0_clk", "rbc0_clk";

		max-clock-frequency-hz = <0 0 100000000

					100000000 300000000 300000000>;

		status = "disabled";

	};

	qcom,wdt@f9017000 {

		compatible = "qcom,msm-watchdog";

		reg = <0xf9017000 0x1000>;