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Commit b47acacd authored by Dhananjay Phadke's avatar Dhananjay Phadke Committed by David S. Miller
Browse files

qlcnic: update oncard memory size check 



All QLogic converged NICs have 128-bit 128MB on card memory.
Fix the limit check from 64MB to 128MB and remove unnecessary
64-bit read/write checks.

Signed-off-by: default avatarDhananjay Phadke <dhananjay.phadke@qlogic.com>
Signed-off-by: default avatarAmit Kumar Salecha <amit.salecha@qlogic.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 897e8c7c

drivers/net/qlcnic/qlcnic_hdr.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -449,7 +449,7 @@ enum { 
#define QLCNIC_ADDR_OCM1	(0x0000000200400000ULL)

#define QLCNIC_ADDR_OCM1	(0x0000000200400000ULL)

#define QLCNIC_ADDR_OCM1_MAX	(0x00000002004fffffULL)

#define QLCNIC_ADDR_OCM1_MAX	(0x00000002004fffffULL)

#define QLCNIC_ADDR_QDR_NET	(0x0000000300000000ULL)

#define QLCNIC_ADDR_QDR_NET	(0x0000000300000000ULL)

#define QLCNIC_ADDR_QDR_NET_MAX_P3 (0x0000000303ffffffULL)

#define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)





/*

/*

 *   Register offsets for MN

 *   Register offsets for MN

drivers/net/qlcnic/qlcnic_hw.c

+24 −31
Original line number Original line Diff line number Diff line
@@ -963,7 +963,6 @@ qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, 
{

{

	int i, j, ret;

	int i, j, ret;

	u32 temp, off8;

	u32 temp, off8;

	u64 stride;

	void __iomem *mem_crb;

	void __iomem *mem_crb;





	/* Only 64-bit aligned access */

	/* Only 64-bit aligned access */
@@ -972,7 +971,7 @@ qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, 




	/* P3 onward, test agent base for MIU and SIU is same */

	/* P3 onward, test agent base for MIU and SIU is same */

	if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,

	if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,

				QLCNIC_ADDR_QDR_NET_MAX_P3)) {

				QLCNIC_ADDR_QDR_NET_MAX)) {

		mem_crb = qlcnic_get_ioaddr(adapter,

		mem_crb = qlcnic_get_ioaddr(adapter,

				QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);

				QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);

		goto correct;

		goto correct;
@@ -990,9 +989,7 @@ qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, 
	return -EIO;

	return -EIO;





correct:

correct:

	stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;

	off8 = off & ~0xf;



	off8 = off & ~(stride-1);





	mutex_lock(&adapter->ahw.mem_lock);

	mutex_lock(&adapter->ahw.mem_lock);
@@ -1000,7 +997,6 @@ correct: 
	writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));

	writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));





	i = 0;

	i = 0;

	if (stride == 16) {

	writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));

	writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));

	writel((TA_CTL_START | TA_CTL_ENABLE),

	writel((TA_CTL_START | TA_CTL_ENABLE),

			(mem_crb + TEST_AGT_CTRL));

			(mem_crb + TEST_AGT_CTRL));
@@ -1022,7 +1018,6 @@ correct: 
	writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),

	writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),

			mem_crb + MIU_TEST_AGT_WRDATA(i+1));

			mem_crb + MIU_TEST_AGT_WRDATA(i+1));

	i = (off & 0xf) ? 2 : 0;

	i = (off & 0xf) ? 2 : 0;

	}





	writel(data & 0xffffffff,

	writel(data & 0xffffffff,

			mem_crb + MIU_TEST_AGT_WRDATA(i));

			mem_crb + MIU_TEST_AGT_WRDATA(i));
@@ -1059,7 +1054,7 @@ qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, 
{

{

	int j, ret;

	int j, ret;

	u32 temp, off8;

	u32 temp, off8;

	u64 val, stride;

	u64 val;

	void __iomem *mem_crb;

	void __iomem *mem_crb;





	/* Only 64-bit aligned access */

	/* Only 64-bit aligned access */
@@ -1068,7 +1063,7 @@ qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, 




	/* P3 onward, test agent base for MIU and SIU is same */

	/* P3 onward, test agent base for MIU and SIU is same */

	if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,

	if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,

				QLCNIC_ADDR_QDR_NET_MAX_P3)) {

				QLCNIC_ADDR_QDR_NET_MAX)) {

		mem_crb = qlcnic_get_ioaddr(adapter,

		mem_crb = qlcnic_get_ioaddr(adapter,

				QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);

				QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);

		goto correct;

		goto correct;
@@ -1088,9 +1083,7 @@ qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, 
	return -EIO;

	return -EIO;





correct:

correct:

	stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;

	off8 = off & ~0xf;



	off8 = off & ~(stride-1);





	mutex_lock(&adapter->ahw.mem_lock);

	mutex_lock(&adapter->ahw.mem_lock);
@@ -1112,7 +1105,7 @@ correct: 
		ret = -EIO;

		ret = -EIO;

	} else {

	} else {

		off8 = MIU_TEST_AGT_RDDATA_LO;

		off8 = MIU_TEST_AGT_RDDATA_LO;

		if ((stride == 16) && (off & 0xf))

		if (off & 0xf)

			off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;

			off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;





		temp = readl(mem_crb + off8 + 4);

		temp = readl(mem_crb + off8 + 4);