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Commit b344c64d authored by Gilad Avidov's avatar Gilad Avidov
Browse files

msm: fsm9900: Add support for GSM NL HW module 



Add support to enable the serial UART port on DIQ connector to
control the GSM NL module. This feature is enabled by default in
fsm9900 targets.

Change-Id: Ief50c896468999121efee882285d16de2da5684f
Acked-by: default avatarJie Luo <jluo@qti.qualcomm.com>
Signed-off-by: default avatarGilad Avidov <gavidov@codeaurora.org>
parent 470c12b7

arch/arm/mach-msm/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -1020,4 +1020,15 @@ config MSM_PP2S_FEMTO 
	  Support for being notified relative to a PP2S pulse

	  Select Y if you want this notification to manifest.

	  If unsure, select N.



config FSM9900_GSM_NL

	bool "FSM9900 GSM NL Hardware Support"

	depends on ARCH_FSM9900

	help

	  Enables the support for GSM NL hardware module. When this option

	  is enabled, the GPIO pins for DIQ interface are configured differently.

	  The DIQ functionality is disabled and the UART functionality is enabled.

	  The serial port connection can be established to communicate with the

	  GSM NL module.



endif

arch/arm/mach-msm/board-fsm9900-gpiomux.c

+31 −13
Original line number Diff line number Diff line
@@ -66,6 +66,20 @@ static struct msm_gpiomux_config fsm_blsp_configs[] __initdata = { 
			[GPIOMUX_SUSPENDED] = &blsp_i2c_config,

		},

	},

#ifdef CONFIG_FSM9900_GSM_NL

	{

		.gpio      = 16,       /* BLSP UART5 TX */

		.settings = {

			[GPIOMUX_SUSPENDED] = &blsp_uart_no_pull_config,

		},

	},

	{

		.gpio      = 17,       /* BLSP UART5 RX */

		.settings = {

			[GPIOMUX_SUSPENDED] = &blsp_uart_pull_up_config,

		},

	},

#endif

	{

		.gpio      = 36,       /* BLSP UART10 TX */

		.settings = {
@@ -169,18 +183,6 @@ static struct msm_gpiomux_config fsm_geni_configs[] __initdata = { 


};



static struct gpiomux_setting dan_spi_func4_config = {

	.func = GPIOMUX_FUNC_4,

	.drv = GPIOMUX_DRV_8MA,

	.pull = GPIOMUX_PULL_UP,

};



static struct gpiomux_setting dan_spi_func1_config = {

	.func = GPIOMUX_FUNC_1,

	.drv = GPIOMUX_DRV_8MA,

	.pull = GPIOMUX_PULL_UP,

};



static struct gpiomux_setting mdm_grfc_config = {

	.func = GPIOMUX_FUNC_2,

	.drv = GPIOMUX_DRV_6MA,
@@ -211,6 +213,19 @@ static struct gpiomux_setting pdm_func1_config = { 
	.pull = GPIOMUX_PULL_UP,

};



#ifndef CONFIG_FSM9900_GSM_NL

static struct gpiomux_setting dan_spi_func4_config = {

	.func = GPIOMUX_FUNC_4,

	.drv = GPIOMUX_DRV_8MA,

	.pull = GPIOMUX_PULL_UP,

};



static struct gpiomux_setting dan_spi_func1_config = {

	.func = GPIOMUX_FUNC_1,

	.drv = GPIOMUX_DRV_8MA,

	.pull = GPIOMUX_PULL_UP,

};



static struct msm_gpiomux_config fsm_dan_spi_configs[] __initdata = {

	{

		.gpio      = 12,       /* BLSP DAN0 SPI_MOSI */
@@ -273,6 +288,7 @@ static struct msm_gpiomux_config fsm_dan_spi_configs[] __initdata = { 
		},

	},

};

#endif



struct msm_gpiomux_config fsm_gluon_grfc_configs[] = {

	{
@@ -979,8 +995,10 @@ void __init fsm9900_init_gpiomux(void) 


	msm_gpiomux_install(fsm_blsp_configs, ARRAY_SIZE(fsm_blsp_configs));

	msm_gpiomux_install(fsm_geni_configs, ARRAY_SIZE(fsm_geni_configs));

#ifndef CONFIG_FSM9900_GSM_NL

	msm_gpiomux_install(fsm_dan_spi_configs,

			    ARRAY_SIZE(fsm_dan_spi_configs));

#endif

	msm_gpiomux_install(fsm_uim_configs, ARRAY_SIZE(fsm_uim_configs));

	msm_gpiomux_install(fsm_pcie_configs, ARRAY_SIZE(fsm_pcie_configs));

	msm_gpiomux_install(fsm_gps_configs, ARRAY_SIZE(fsm_gps_configs));

arch/arm/mach-msm/clock-fsm9900.c

+2 −0
Original line number Diff line number Diff line
@@ -2721,8 +2721,10 @@ static struct clk_lookup fsm_clocks_9900[] = { 


	/* BLSP1  clocks. Only the valid configs are present in the table */

	CLK_LOOKUP("iface_clk",	gcc_blsp1_ahb_clk.c,	"f991f000.serial"),

	CLK_LOOKUP("iface_clk",	gcc_blsp1_ahb_clk.c,	"f9921000.serial"),

	CLK_LOOKUP("iface_clk",	gcc_blsp1_ahb_clk.c,	"f9924000.i2c"),

	CLK_LOOKUP("core_clk",	gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"),

	CLK_LOOKUP("core_clk",	gcc_blsp1_uart5_apps_clk.c, "f9921000.serial"),

	CLK_LOOKUP("core_clk",	gcc_blsp1_qup2_i2c_apps_clk.c, "f9924000.i2c"),



	/* BLSP2  clocks. Only the valid configs are present in the table */