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Commit b2f4b65a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

ARM: arch_timer: resurrect cntpct for MSM users 



We have some users of the physical counter reading function, and
they need to work when either the cp15 or mmio timers are present
in any configuration. Bring back the functionality and expose it
to drivers so that the RPM code and SMEM code have proper global
timestamps to communicate with other processors.

Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent cc463a89

arch/arm/include/asm/arch_timer.h

+10 −1
Original line number Diff line number Diff line
@@ -81,7 +81,16 @@ static inline u32 arch_timer_get_cntfrq(void) 
	return val;

}



static inline u64 arch_counter_get_cntvct(void)

static inline u64 arch_counter_get_cntpct_cp15(void)

{

	u64 cval;



	isb();

	asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));

	return cval;

}



static inline u64 arch_counter_get_cntvct_cp15(void)

{

	u64 cval;

arch/arm64/include/asm/arch_timer.h

+1 −1
Original line number Diff line number Diff line
@@ -110,7 +110,7 @@ static inline void __cpuinit arch_counter_set_user_access(void) 
	asm volatile("msr	cntkctl_el1, %0" : : "r" (cntkctl));

}



static inline u64 arch_counter_get_cntvct(void)

static inline u64 arch_counter_get_cntvct_cp15(void)

{

	u64 cval;

drivers/clocksource/arm_arch_timer.c

+30 −2
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 
#define CNTTIDR		0x08

#define CNTTIDR_VIRT(n)	(BIT(1) << ((n) * 4))



#define CNTPCT_LO	0x00

#define CNTPCT_HI	0x04

#define CNTVCT_LO	0x08

#define CNTVCT_HI	0x0c

#define CNTFRQ		0x10
@@ -362,6 +364,19 @@ u32 arch_timer_get_rate(void) 
	return arch_timer_rate;

}



static u64 arch_counter_get_cntpct_mem(void)

{

	u32 pct_lo, pct_hi, tmp_hi;



	do {

		pct_hi = readl_relaxed(arch_counter_base + CNTPCT_HI);

		pct_lo = readl_relaxed(arch_counter_base + CNTPCT_LO);

		tmp_hi = readl_relaxed(arch_counter_base + CNTPCT_HI);

	} while (pct_hi != tmp_hi);



	return ((u64) pct_hi << 32) | pct_lo;

}



static u64 arch_counter_get_cntvct_mem(void)

{

	u32 vct_lo, vct_hi, tmp_hi;
@@ -381,7 +396,7 @@ static u64 arch_counter_get_cntvct_mem(void) 
 * to exist on arm64. arm doesn't use this before DT is probed so even

 * if we don't have the cp15 accessors we won't have a problem.

 */

u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;

u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct_cp15;



static cycle_t arch_counter_read(struct clocksource *cs)

{
@@ -393,6 +408,19 @@ static cycle_t arch_counter_read_cc(const struct cyclecounter *cc) 
	return arch_timer_read_counter();

}



u64 arch_counter_get_cntpct(void)

{

	if (arch_timer_read_counter == arch_counter_get_cntvct_cp15)

		return arch_counter_get_cntpct_cp15();

	else

		return arch_counter_get_cntpct_mem();

}



u64 arch_counter_get_cntvct(void)

{

	return arch_timer_read_counter();

}



static struct clocksource clocksource_counter = {

	.name	= "arch_sys_counter",

	.rating	= 400,
@@ -419,7 +447,7 @@ static void __init arch_counter_register(unsigned type) 


	/* Register the CP15 based counter if we have one */

	if (type & ARCH_CP15_TIMER)

		arch_timer_read_counter = arch_counter_get_cntvct;

		arch_timer_read_counter = arch_counter_get_cntvct_cp15;

	else

		arch_timer_read_counter = arch_counter_get_cntvct_mem;

include/clocksource/arm_arch_timer.h

+6 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ 
extern u32 arch_timer_get_rate(void);

extern u64 (*arch_timer_read_counter)(void);

extern struct timecounter *arch_timer_get_timecounter(void);

extern u64 arch_counter_get_cntpct(void);

extern u64 arch_counter_get_cntvct(void);



#else
@@ -54,6 +56,10 @@ static inline struct timecounter *arch_timer_get_timecounter(void) 
	return NULL;

}



static inline u64 arch_counter_get_cntpct(void) { return 0; }



static inline u64 arch_counter_get_cntvct(void) { return 0; }



#endif



#endif