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Commit b246f199 authored by Yan He's avatar Yan He
Browse files

msm: 8084: Enable PCIe RCs with clock and board support 



Update PCIe clock mapping and auxdata lookup entries when two PCIe
Root Complexes (RCs) on APQ8084 are both used.

Change-Id: I6b8a2314c7cf8a3f6473850b23fd092f7596863e
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent 458a0fb6

arch/arm/mach-msm/board-8084.c

+2 −2
Original line number Diff line number Diff line
@@ -67,8 +67,8 @@ static struct of_dev_auxdata apq8084_auxdata_lookup[] __initdata = { 
	OF_DEV_AUXDATA("qca,qca1530", 0x00000000, "qca1530.1", NULL),

	OF_DEV_AUXDATA("qcom,ufshc", 0xFC594000, "msm_ufs.1", NULL),

	OF_DEV_AUXDATA("qcom,xhci-msm-hsic", 0xf9c00000, "msm_hsic_host", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC520000, "msm_pcie", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC528000, "msm_pcie", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC520000, "msm_pcie.1", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC528000, "msm_pcie.2", NULL),

	{}

};

arch/arm/mach-msm/clock-8084.c

+17 −14
Original line number Diff line number Diff line
@@ -6057,21 +6057,24 @@ static struct clk_lookup apq_clocks_8084[] = { 
	CLK_LOOKUP("",	gcc_usb3_phy_clk.c,	""),



	/* PCIE clocks */

	CLK_LOOKUP("pcie_0_aux_clk", gcc_pcie_0_aux_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_cfg_ahb_clk", gcc_pcie_0_cfg_ahb_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_aux_clk", gcc_pcie_0_aux_clk.c, "msm_pcie.1"),

	CLK_LOOKUP("pcie_0_cfg_ahb_clk", gcc_pcie_0_cfg_ahb_clk.c,

			"msm_pcie.1"),

	CLK_LOOKUP("pcie_0_mstr_axi_clk", gcc_pcie_0_mstr_axi_clk.c,

			"msm_pcie"),

	CLK_LOOKUP("pcie_0_pipe_clk", gcc_pcie_0_pipe_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_slv_axi_clk", gcc_pcie_0_slv_axi_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_ref_clk_src", rf_clk3.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_aux_clk", gcc_pcie_1_aux_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_cfg_ahb_clk", gcc_pcie_1_cfg_ahb_clk.c, "msm_pcie"),

			"msm_pcie.1"),

	CLK_LOOKUP("pcie_0_pipe_clk", gcc_pcie_0_pipe_clk.c, "msm_pcie.1"),

	CLK_LOOKUP("pcie_0_slv_axi_clk", gcc_pcie_0_slv_axi_clk.c,

			"msm_pcie.1"),

	CLK_LOOKUP("pcie_0_ref_clk_src", rf_clk3.c, "msm_pcie.1"),

	CLK_LOOKUP("pcie_1_aux_clk", gcc_pcie_1_aux_clk.c, "msm_pcie.2"),

	CLK_LOOKUP("pcie_1_cfg_ahb_clk", gcc_pcie_1_cfg_ahb_clk.c,

			"msm_pcie.2"),

	CLK_LOOKUP("pcie_1_mstr_axi_clk", gcc_pcie_1_mstr_axi_clk.c,

			"msm_pcie"),

	CLK_LOOKUP("pcie_1_pipe_clk", gcc_pcie_1_pipe_clk.c, "msm_pcie"),

			"msm_pcie.2"),

	CLK_LOOKUP("pcie_1_pipe_clk", gcc_pcie_1_pipe_clk.c, "msm_pcie.2"),

	CLK_LOOKUP("pcie_1_slv_axi_clk", gcc_pcie_1_slv_axi_clk.c,

			"msm_pcie"),

	CLK_LOOKUP("pcie_1_ref_clk_src", rf_clk3.c, "msm_pcie"),

			"msm_pcie.2"),

	CLK_LOOKUP("pcie_1_ref_clk_src", rf_clk3.c, "msm_pcie.2"),



	/* CoreSight clocks */

	CLK_LOOKUP("core_clk", qdss_clk.c, "fc326000.tmc"),
@@ -6577,8 +6580,8 @@ static struct clk_lookup apq_clocks_8084[] = { 
	CLK_LOOKUP("",		byte_clk_src_8084.c,               ""),



	/* LDO */

	CLK_LOOKUP("pcie_0_ldo",	pcie_0_phy_ldo.c,  "msm_pcie"),

	CLK_LOOKUP("pcie_1_ldo",	pcie_1_phy_ldo.c,  "msm_pcie"),

	CLK_LOOKUP("pcie_0_ldo",	pcie_0_phy_ldo.c,  "msm_pcie.1"),

	CLK_LOOKUP("pcie_1_ldo",	pcie_1_phy_ldo.c,  "msm_pcie.2"),

	CLK_LOOKUP("",		sata_phy_ldo.c,               ""),



	CLK_LOOKUP("qca,rtc_clk",	div_clk3.c, "qca1530.1"),