clock-mmss-8994: Fix source for pclk1_clk_src



pclk1_clk_src still uses DSI0 PLL as clock source. Fix the src_clk
to use DSI0 PLL.

Change-Id: I0f124074001e6fb7f45de364d350346cad315e14
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>

parent f9e5104e

drivers/clk/qcom/clock-mmss-8994.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -675,7 +675,7 @@ static struct rcg_clk pclk0_clk_src = {

		static struct clk_freq_tbl ftbl_pclk1_clk_src[] = {
		{
		.div_src_val = BVAL(10, 8, dsi1phypll_mm_source_val)
		.div_src_val = BVAL(10, 8, dsi0phypll_mm_source_val)
		\| BVAL(4, 0, 0),
		},
		F_END