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Commit b1823e6d authored by Tarun Karra's avatar Tarun Karra Committed by Jordan Crouse
Browse files

msm: kgsl: Add content protection changes for A430 



Add Content protection changes to increase register range to access
secvid registers, check if content protection is supported by
parsing device tree, flush HLSQ in secure mode for secure buffer,
skip programming secure context bank registers and create secure
pagetable with secure domain.

Change-Id: Ic96490b45cc70bce282a28e420f3fb4e175e95ad
Signed-off-by: default avatarTarun Karra <tkarra@codeaurora.org>
parent 9f25a3ef

arch/arm/boot/dts/qcom/msm8994-gpu.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -19,9 +19,8 @@ 
	msm_gpu: qcom,kgsl-3d0@fdb00000 {

		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		reg = <0xfdb00000 0x20000

		       0xfdb20000 0x10000>;

		reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";

		reg = <0xfdb00000 0x40000>;

		reg-names = "kgsl_3d0_reg_memory";

		interrupts = <0 33 0>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;

drivers/gpu/msm/a4xx_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -440,6 +440,8 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_RBBM_PPD_EPOCH_INTRA_TH_2		0x1bb

#define A4XX_RBBM_PPD_EPOCH_INTER_TH_HI_CLR_TH  0x1bc

#define A4XX_RBBM_PPD_EPOCH_INTER_TH_LO         0x1bd

/* SECVID registers */

#define A4XX_RBBM_SECVID_TRUST_CONFIG		0xf000

#define A4XX_RBBM_SECVID_TRUST_CONTROL		0xf400

#define A4XX_RBBM_SECVID_TSB_TRUSTED_BASE	0xf800

#define A4XX_RBBM_SECVID_TSB_TRUSTED_SIZE	0xf801

drivers/gpu/msm/adreno-gpulist.h

+2 −1
Original line number Diff line number Diff line
@@ -179,7 +179,8 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM  | ADRENO_WARM_START |

			ADRENO_USE_BOOTSTRAP | ADRENO_SPTP_PC | ADRENO_PPD,

			ADRENO_USE_BOOTSTRAP | ADRENO_SPTP_PC | ADRENO_PPD |

			ADRENO_CONTENT_PROTECTION,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

drivers/gpu/msm/adreno.c

+27 −10
Original line number Diff line number Diff line
@@ -584,9 +584,19 @@ done: 


}



static int adreno_of_get_iommu(struct device_node *parent,

static inline struct adreno_device *adreno_get_dev(struct platform_device *pdev)

{

	const struct of_device_id *of_id =

		of_match_device(adreno_match_table, &pdev->dev);



	return of_id ? (struct adreno_device *) of_id->data : NULL;

}



static int adreno_of_get_iommu(struct platform_device *pdev,

	struct kgsl_device_platform_data *pdata)

{

	struct device_node *parent = pdev->dev.of_node;

	struct adreno_device *adreno_dev = adreno_get_dev(pdev);

	int result = -EINVAL;

	struct device_node *node, *child;

	struct kgsl_device_iommu_data *data = NULL;
@@ -598,6 +608,10 @@ static int adreno_of_get_iommu(struct device_node *parent, 
	if (node == NULL)

		return -EINVAL;



	if (adreno_dev)

		adreno_dev->dev.mmu.secured =

			of_property_read_bool(node, "qcom,iommu-secure-id");



	data = kzalloc(sizeof(*data), GFP_KERNEL);

	if (data == NULL) {

		result = -ENOMEM;
@@ -718,7 +732,7 @@ static int adreno_of_get_pdata(struct platform_device *pdev) 
		goto err;

	}



	ret = adreno_of_get_iommu(pdev->dev.of_node, pdata);

	ret = adreno_of_get_iommu(pdev, pdata);

	if (ret)

		goto err;
@@ -784,14 +798,6 @@ adreno_ocmem_free(struct adreno_device *adreno_dev) 
}

#endif



static inline struct adreno_device *adreno_get_dev(struct platform_device *pdev)

{

	const struct of_device_id *of_id =

		of_match_device(adreno_match_table, &pdev->dev);



	return of_id ? (struct adreno_device *) of_id->data : NULL;

}



int adreno_probe(struct platform_device *pdev)

{

	struct kgsl_device *device;
@@ -817,6 +823,17 @@ int adreno_probe(struct platform_device *pdev) 
	/* Identify the specific GPU */

	adreno_identify_gpu(adreno_dev);



	/*

	 * qcom,iommu-secure-id is used to identify MMUs that can handle secure

	 * content but that is only part of the story - the GPU also has to be

	 * able to handle secure content.  Unfortunately in a classic catch-22

	 * we cannot identify the GPU until after the DT is parsed. tl;dr -

	 * check the GPU capabilities here and modify mmu->secured accordingly

	 */



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_CONTENT_PROTECTION))

		device->mmu.secured = false;



	status = kgsl_device_platform_probe(device);

	if (status) {

		device->pdev = NULL;

drivers/gpu/msm/adreno.h

+2 −0
Original line number Diff line number Diff line
@@ -81,6 +81,8 @@ 
#define ADRENO_PPD BIT(6)

/* The microcode supports register to register copy and compare */

#define ADRENO_HAS_REG_TO_REG_CMDS BIT(7)

/* The GPU supports content protection */

#define ADRENO_CONTENT_PROTECTION BIT(8)



/* Flags to control command packet settings */

#define KGSL_CMD_FLAGS_NONE             0