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Commit b115e4fd authored by Xiaocheng Li's avatar Xiaocheng Li
Browse files

ARM: msm: Update MPIDR mask for ARMV8-32bit support 



In ARMv8, MPIDR bit[0:23] are all used for multi-clusters support,
so update the MPIDR mask accordingly.

Change-Id: Iae5a2308e7c854a5e85746dffbce7715cf86d86b
Signed-off-by: default avatarXiaocheng Li <lix@codeaurora.org>
Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
parent 2b979b24

arch/arm/mach-msm/headsmp.S

+2 −2
Original line number Diff line number Diff line 
/*

 *  Copyright (c) 2003 ARM Limited

 *  All Rights Reserved

 *  Copyright (c) 2010, 2012 The Linux Foundation. All rights reserved.

 *  Copyright (c) 2010, 2012, 2014 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -27,7 +27,7 @@ THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 
THUMB(	.thumb			)	@ switch to Thumb now.

THUMB(2:			)

	mrc	p15, 0, r0, c0, c0, 5 	@ MPIDR

	and	r0, r0, #15		@ What CPU am I

	bic     r0, #0xff000000         @ What CPU am I

	adr	r4, 1f			@ address of

	ldmia	r4, {r5, r6}		@ load curr addr and pen_rel addr

	sub	r4, r4, r5		@ determine virtual/phys offsets

drivers/soc/qcom/idle-v7.S

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 * Idle processing for ARMv7-based Qualcomm SoCs.

 *

 * Copyright (C) 2007 Google, Inc.

 * Copyright (c) 2007-2009, 2011-2013 The Linux Foundation. All rights reserved.

 * Copyright (c) 2007-2009, 2011-2014 The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -26,7 +26,7 @@ THUMB( bx r9 ) /* If this is a Thumb-2 kernel, */ 
THUMB(	.thumb			)	/* switch to Thumb now.		*/

THUMB(2:			)

	mrc     p15, 0, r0, c0, c0, 5    /* MPIDR                          */

	and     r0, r0, #15              /* what CPU am I                  */

	bic     r0, #0xff000000         /* what CPU am I                  */



	adr	r3, 3f

	ldr	r1, [r3]