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Commit b0c884a3 authored by Dhaval Patel's avatar Dhaval Patel
Browse files

msm: mdss: Support six zone and memory color access 



Allow display calibration tool to access six zone and
memory color area on MDSS hardware for 8084 target.

Change-Id: I6c5e180448dc0218bdf6e552a12ced8914316c60
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent abedad47

drivers/video/msm/mdss/mdss_mdp_hwio.h

+1 −0
Original line number Diff line number Diff line
@@ -438,6 +438,7 @@ enum mdss_mdp_dspp_index { 
#define MDSS_MDP_REG_DSPP_HIST_CTL_BASE			0x210

#define MDSS_MDP_REG_DSPP_HIST_LUT_BASE			0x230

#define MDSS_MDP_REG_DSPP_PA_BASE			0x238

#define MDSS_MDP_REG_DSPP_SIX_ZONE_BASE			0x248

#define MDSS_MDP_REG_DSPP_GAMUT_BASE			0x2DC

#define MDSS_MDP_REG_DSPP_GC_BASE			0x2B0

drivers/video/msm/mdss/mdss_mdp_pp.c

+17 −0
Original line number Diff line number Diff line
@@ -174,6 +174,8 @@ static u32 igc_limited[IGC_LUT_ENTRIES] = { 
	GAMUT_T5_SIZE + GAMUT_T6_SIZE + GAMUT_T7_SIZE)



#define MDSS_MDP_PA_SIZE		0xC

#define MDSS_MDP_SIX_ZONE_SIZE		0xC

#define MDSS_MDP_MEM_COL_SIZE		0x3C

#define MDSS_MDP_GC_SIZE		0x28

#define MDSS_MDP_PCC_SIZE		0xB8

#define MDSS_MDP_GAMUT_SIZE		0x5C
@@ -4342,6 +4344,14 @@ static int is_valid_calib_dspp_addr(char __iomem *ptr) 
		} else if ((ptr == base + MDSS_MDP_REG_DSPP_DITHER_DEPTH)) {

			ret = MDP_PP_OPS_READ | MDP_PP_OPS_WRITE;

			break;

		/* Six zone and mem color */

		} else if (mdss_res->mdp_rev >= MDSS_MDP_HW_REV_103 &&

			(ptr >= base + MDSS_MDP_REG_DSPP_SIX_ZONE_BASE) &&

			(ptr <= base + MDSS_MDP_REG_DSPP_SIX_ZONE_BASE +

					MDSS_MDP_SIX_ZONE_SIZE +

					MDSS_MDP_MEM_COL_SIZE)) {

			ret = MDP_PP_OPS_READ | MDP_PP_OPS_WRITE;

			break;

		}

	}
@@ -4376,6 +4386,13 @@ static int is_valid_calib_vig_addr(char __iomem *ptr) 
						MDSS_MDP_PA_SIZE)) {

			ret = MDP_PP_OPS_READ | MDP_PP_OPS_WRITE;

			break;

		/* Mem color range */

		} else if (mdss_res->mdp_rev >= MDSS_MDP_HW_REV_103 &&

			(ptr >= base + MDSS_MDP_REG_VIG_MEM_COL_BASE) &&

				(ptr <= base + MDSS_MDP_REG_VIG_MEM_COL_BASE +

						MDSS_MDP_MEM_COL_SIZE)) {

			ret = MDP_PP_OPS_READ | MDP_PP_OPS_WRITE;

			break;

		/* IGC range */

		} else if ((ptr >= base + MDSS_MDP_REG_IGC_VIG_BASE) &&

				(ptr <= base + MDSS_MDP_REG_IGC_VIG_BASE +