Loading drivers/video/msm/mdss/mdss_fb.c +11 −0 Original line number Diff line number Diff line Loading @@ -2929,6 +2929,17 @@ static void mdss_fb_var_to_panelinfo(struct fb_var_screeninfo *var, pinfo->lcdc.h_front_porch = var->right_margin; pinfo->lcdc.h_back_porch = var->left_margin; pinfo->lcdc.h_pulse_width = var->hsync_len; if (var->sync & FB_SYNC_HOR_HIGH_ACT) pinfo->lcdc.h_polarity = 0; else pinfo->lcdc.h_polarity = 1; if (var->sync & FB_SYNC_VERT_HIGH_ACT) pinfo->lcdc.v_polarity = 0; else pinfo->lcdc.v_polarity = 1; pinfo->clk_rate = var->pixclock; } Loading drivers/video/msm/mdss/mdss_hdmi_tx.c +2 −0 Original line number Diff line number Diff line Loading @@ -1352,9 +1352,11 @@ static int hdmi_tx_init_panel_info(struct hdmi_tx_ctrl *hdmi_ctrl) pinfo->lcdc.h_back_porch = timing.back_porch_h; pinfo->lcdc.h_front_porch = timing.front_porch_h; pinfo->lcdc.h_pulse_width = timing.pulse_width_h; pinfo->lcdc.h_polarity = timing.active_low_h; pinfo->lcdc.v_back_porch = timing.back_porch_v; pinfo->lcdc.v_front_porch = timing.front_porch_v; pinfo->lcdc.v_pulse_width = timing.pulse_width_v; pinfo->lcdc.v_polarity = timing.active_low_v; pinfo->type = DTV_PANEL; pinfo->pdest = DISPLAY_2; Loading drivers/video/msm/mdss/mdss_mdp_intf_video.c +6 −7 Original line number Diff line number Diff line Loading @@ -46,6 +46,8 @@ struct intf_timing_params { u32 v_front_porch; u32 hsync_pulse_width; u32 vsync_pulse_width; u32 h_polarity; u32 v_polarity; u32 border_clr; u32 underflow_clr; Loading Loading @@ -286,13 +288,8 @@ static int mdss_mdp_video_timegen_setup(struct mdss_mdp_ctl *ctl, display_hctl = (hsync_end_x << 16) | hsync_start_x; den_polarity = 0; if (MDSS_INTF_HDMI == ctx->intf_type) { hsync_polarity = p->yres >= 720 ? 0 : 1; vsync_polarity = p->yres >= 720 ? 0 : 1; } else { hsync_polarity = 0; vsync_polarity = 0; } hsync_polarity = p->h_polarity; vsync_polarity = p->v_polarity; polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ (vsync_polarity << 1) | /* VSYNC Polarity */ (hsync_polarity << 0); /* HSYNC Polarity */ Loading Loading @@ -1255,6 +1252,8 @@ static int mdss_mdp_video_ctx_setup(struct mdss_mdp_ctl *ctl, itp.v_front_porch = pinfo->lcdc.v_front_porch; itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; itp.h_polarity = pinfo->lcdc.h_polarity; itp.v_polarity = pinfo->lcdc.v_polarity; if (!ctl->panel_data->panel_info.cont_splash_enabled) { if (mdss_mdp_video_timegen_setup(ctl, &itp, ctx)) { Loading drivers/video/msm/mdss/mdss_panel.h +2 −0 Original line number Diff line number Diff line Loading @@ -238,6 +238,8 @@ struct lcd_panel_info { u32 xres_pad; /* Pad height */ u32 yres_pad; u32 h_polarity; u32 v_polarity; }; Loading Loading
drivers/video/msm/mdss/mdss_fb.c +11 −0 Original line number Diff line number Diff line Loading @@ -2929,6 +2929,17 @@ static void mdss_fb_var_to_panelinfo(struct fb_var_screeninfo *var, pinfo->lcdc.h_front_porch = var->right_margin; pinfo->lcdc.h_back_porch = var->left_margin; pinfo->lcdc.h_pulse_width = var->hsync_len; if (var->sync & FB_SYNC_HOR_HIGH_ACT) pinfo->lcdc.h_polarity = 0; else pinfo->lcdc.h_polarity = 1; if (var->sync & FB_SYNC_VERT_HIGH_ACT) pinfo->lcdc.v_polarity = 0; else pinfo->lcdc.v_polarity = 1; pinfo->clk_rate = var->pixclock; } Loading
drivers/video/msm/mdss/mdss_hdmi_tx.c +2 −0 Original line number Diff line number Diff line Loading @@ -1352,9 +1352,11 @@ static int hdmi_tx_init_panel_info(struct hdmi_tx_ctrl *hdmi_ctrl) pinfo->lcdc.h_back_porch = timing.back_porch_h; pinfo->lcdc.h_front_porch = timing.front_porch_h; pinfo->lcdc.h_pulse_width = timing.pulse_width_h; pinfo->lcdc.h_polarity = timing.active_low_h; pinfo->lcdc.v_back_porch = timing.back_porch_v; pinfo->lcdc.v_front_porch = timing.front_porch_v; pinfo->lcdc.v_pulse_width = timing.pulse_width_v; pinfo->lcdc.v_polarity = timing.active_low_v; pinfo->type = DTV_PANEL; pinfo->pdest = DISPLAY_2; Loading
drivers/video/msm/mdss/mdss_mdp_intf_video.c +6 −7 Original line number Diff line number Diff line Loading @@ -46,6 +46,8 @@ struct intf_timing_params { u32 v_front_porch; u32 hsync_pulse_width; u32 vsync_pulse_width; u32 h_polarity; u32 v_polarity; u32 border_clr; u32 underflow_clr; Loading Loading @@ -286,13 +288,8 @@ static int mdss_mdp_video_timegen_setup(struct mdss_mdp_ctl *ctl, display_hctl = (hsync_end_x << 16) | hsync_start_x; den_polarity = 0; if (MDSS_INTF_HDMI == ctx->intf_type) { hsync_polarity = p->yres >= 720 ? 0 : 1; vsync_polarity = p->yres >= 720 ? 0 : 1; } else { hsync_polarity = 0; vsync_polarity = 0; } hsync_polarity = p->h_polarity; vsync_polarity = p->v_polarity; polarity_ctl = (den_polarity << 2) | /* DEN Polarity */ (vsync_polarity << 1) | /* VSYNC Polarity */ (hsync_polarity << 0); /* HSYNC Polarity */ Loading Loading @@ -1255,6 +1252,8 @@ static int mdss_mdp_video_ctx_setup(struct mdss_mdp_ctl *ctl, itp.v_front_porch = pinfo->lcdc.v_front_porch; itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; itp.h_polarity = pinfo->lcdc.h_polarity; itp.v_polarity = pinfo->lcdc.v_polarity; if (!ctl->panel_data->panel_info.cont_splash_enabled) { if (mdss_mdp_video_timegen_setup(ctl, &itp, ctx)) { Loading
drivers/video/msm/mdss/mdss_panel.h +2 −0 Original line number Diff line number Diff line Loading @@ -238,6 +238,8 @@ struct lcd_panel_info { u32 xres_pad; /* Pad height */ u32 yres_pad; u32 h_polarity; u32 v_polarity; }; Loading