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Commit af7ae351 authored by Maciej Cencora's avatar Maciej Cencora Committed by Dave Airlie
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drm/radeon: add regs required for occlusion queries support



[airlied: cleaned up slightly for drm-next]

Signed-off-by: default avatarMaciej Cencora <m.cencora@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent d0088775
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+5 −0
Original line number Diff line number Diff line
@@ -207,6 +207,10 @@ void r300_init_reg_flags(struct drm_device *dev)
	ADD_RANGE(0x42C0, 2);
	ADD_RANGE(R300_RS_CNTL_0, 2);

	ADD_RANGE(R300_SU_REG_DEST, 1);
	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530)
		ADD_RANGE(RV530_FG_ZBREG_DEST, 1);

	ADD_RANGE(R300_SC_HYPERZ, 2);
	ADD_RANGE(0x43E8, 1);

@@ -232,6 +236,7 @@ void r300_init_reg_flags(struct drm_device *dev)
	ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
	ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
	ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
	ADD_RANGE(R300_ZB_ZPASS_DATA, 2); /* ZB_ZPASS_DATA, ZB_ZPASS_ADDR */

	ADD_RANGE(R300_TX_FILTER_0, 16);
	ADD_RANGE(R300_TX_FILTER1_0, 16);
+5 −0
Original line number Diff line number Diff line
@@ -1770,4 +1770,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R500_RB3D_COLOR_CLEAR_VALUE_AR  0x46c0
#define R500_RB3D_CONSTANT_COLOR_AR     0x4ef8

#define R300_SU_REG_DEST                0x42c8
#define RV530_FG_ZBREG_DEST             0x4be8
#define R300_ZB_ZPASS_DATA              0x4f58
#define R300_ZB_ZPASS_ADDR              0x4f5c

#endif /* _R300_REG_H */
+1 −1
Original line number Diff line number Diff line
@@ -434,7 +434,7 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)

	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
		RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
		RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
		RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
	}
	RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
	radeon_do_wait_for_idle(dev_priv);
+0 −1
Original line number Diff line number Diff line
@@ -687,7 +687,6 @@ extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pciga
/* pipe config regs */
#define R400_GB_PIPE_SELECT             0x402c
#define R500_DYN_SCLK_PWMEM_PIPE        0x000d /* PLL */
#define R500_SU_REG_DEST                0x42c8
#define R300_GB_TILE_CONFIG             0x4018
#       define R300_ENABLE_TILING       (1 << 0)
#       define R300_PIPE_COUNT_RV350    (0 << 1)