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Commit ae186e21 authored by Patrick Daly's avatar Patrick Daly Committed by Deepak Katragadda
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clk: clock-local2: Support parsing cbc clocks from dt 



cbc clocks allow for power savings by gating clock signals.

Change-Id: I7b160a4eb0445e32ed4029be56307c87b2887373
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent c1a5a21e

Documentation/devicetree/bindings/arm/msm/clock-controller-v2.txt

+34 −0
Original line number Diff line number Diff line
@@ -218,3 +218,37 @@ bb_clk2_a: bb_clk2_a { 
	qcom,rpm-peer = <&bb_clk2>;

	qcom,rcg-init-rate = <1000>;

};



*****************************************************************************

"qcom,cbc"



CBC clocks are a set of hw registers which can gate a clock signal. Additionally,

a feedback signal is available which indicates whether the clock is actually on or

off. This signal can be used by software to determine how much time to delay after

requesting that the clock be turned on/off.



Required Properties:

- compatible		Must be "qcom,cbc".



- qcom,base-offset:	Offset from the register region described in the parent

			clock controller.



Recommended Properties:

- qcom,parent:		See "General Optional Properties"



Optional Properties:

- qcom,bcr-offset:	Offset from the register region described in the parent

			clock controller for the reset.



- qcom,has-sibling:	Boolean.

			This clock does not have permission to change its parent's rate.

			For example, there may be several cbc clocks which share the

			same parent. Thus changing the rate of one of the cbcs would

			affect all.



ocmemcx_ahb_clk: ocmemcx_ahb_clk {

	compatible = "qcom,cbc";

	qcom,base-offset = <MMSS_OCMEMCX_AHB_CBCR>;

	qcom,has-sibling;

	qcom,parent = <&mmssnoc_ahb_clk>;

};

drivers/clk/qcom/clock-local2.c

+37 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include <linux/clk/msm-clk.h>

#include <linux/clk/msm-clock-generic.h>

#include <soc/qcom/clock-local2.h>

#include <soc/qcom/msm-clock-controller.h>



/*

 * When enabling/disabling a clock, check the halt bit up to this number
@@ -1507,3 +1508,39 @@ struct mux_div_ops rcg_mux_div_ops = { 
	.is_enabled = rcg_is_enabled,

	.list_registers = rcg_list_registers,

};



static void *cbc_dt_parser(struct device *dev, struct device_node *np)

{

	struct msmclk_data *drv;

	struct branch_clk *branch_clk;

	u32 rc;



	branch_clk = devm_kzalloc(dev, sizeof(*branch_clk), GFP_KERNEL);

	if (!branch_clk) {

		dt_err(np, "memory alloc failure\n");

		return ERR_PTR(-ENOMEM);

	}



	drv = msmclk_parse_phandle(dev, np->parent->phandle);

	if (IS_ERR_OR_NULL(drv))

		return ERR_CAST(drv);

	branch_clk->base = &drv->base;



	rc = of_property_read_u32(np, "qcom,base-offset",

						&branch_clk->cbcr_reg);

	if (rc) {

		dt_err(np, "missing/incorrect qcom,base-offset dt property\n");

		return ERR_PTR(rc);

	}



	/* Optional property */

	of_property_read_u32(np, "qcom,bcr-offset", &branch_clk->bcr_reg);



	branch_clk->has_sibling = of_property_read_bool(np,

							"qcom,has-sibling");



	branch_clk->c.ops = &clk_ops_branch;



	return msmclk_generic_clk_init(dev, np, &branch_clk->c);

}

MSMCLK_PARSER(cbc_dt_parser, "qcom,cbc", 0);

include/soc/qcom/clock-local2.h

+2 −2
Original line number Diff line number Diff line
@@ -90,8 +90,8 @@ extern struct clk_freq_tbl rcg_dummy_freq; 
struct branch_clk {

	void   (*set_rate)(struct branch_clk *, struct clk_freq_tbl *);

	struct clk c;

	const u32 cbcr_reg;

	const u32 bcr_reg;

	u32 cbcr_reg;

	u32 bcr_reg;

	int has_sibling;

	u32 cur_div;

	u32 max_div;