Loading arch/arm/boot/dts/qcom/apq8084.dtsi +16 −1 Original line number Diff line number Diff line Loading @@ -2535,7 +2535,7 @@ < 2265600000 950000 726 >; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>; qcom,bw-tbl = Loading @@ -2560,6 +2560,21 @@ qcom,bytes-per-beat = <16>; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 300000 1144 >, < 422400 2288 >, < 652800 3051 >, < 883200 5996 >, < 1190400 8056 >, < 1497600 10101 >, < 1728000 12145 >, < 2649600 16250 >; }; }; qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", Loading arch/arm/boot/dts/qcom/fsm9900.dtsi +13 −1 Original line number Diff line number Diff line Loading @@ -663,7 +663,7 @@ "tsens_tz_sensor5", "tsens_tz_sensor6"; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>, <2 512>; qcom,bw-tbl = Loading @@ -674,6 +674,18 @@ < 6103 /* 800 MHz */ >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 300000 572 >, < 422400 1144 >, < 883200 2342 >, < 1190400 3509 >, < 2265600 6103 >; }; }; qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", Loading arch/arm/boot/dts/qcom/mdm9630.dtsi +11 −1 Original line number Diff line number Diff line Loading @@ -751,7 +751,7 @@ cpu-vdd-supply = <&pmd9635_l3_corner_ao>; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>; qcom,bw-tbl = Loading @@ -760,6 +760,16 @@ < 3051 /* 400 MHz */ >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 600000 1266 >, < 787200 2540 >, < 1152000 3051 >; }; }; qcom,msm-cpufreq@0 { reg = <0 4>; compatible = "qcom,msm-cpufreq"; Loading arch/arm/boot/dts/qcom/msm8226.dtsi +10 −1 Original line number Diff line number Diff line Loading @@ -1004,7 +1004,7 @@ cpu-vdd-supply = <&apc_vreg_corner>; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>; qcom,bw-tbl = Loading @@ -1014,6 +1014,15 @@ < 4066 /* 533 MHz */ >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 787200 1525 >, < 1785600 4066 >; }; }; qcom,msm-cpufreq@0 { reg = <0 4>; compatible = "qcom,msm-cpufreq"; Loading arch/arm/boot/dts/qcom/msm8610.dtsi +11 −1 Original line number Diff line number Diff line Loading @@ -514,7 +514,7 @@ cpu-vdd-supply = <&apc_vreg_corner>; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>; qcom,bw-tbl = Loading @@ -523,6 +523,16 @@ < 2540 /* 333 MHz */ >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 384000 762 >, < 787200 1525 >, < 1190400 2540 >; }; }; qcom,msm-cpufreq@0 { reg = <0 4>; compatible = "qcom,msm-cpufreq"; Loading Loading
arch/arm/boot/dts/qcom/apq8084.dtsi +16 −1 Original line number Diff line number Diff line Loading @@ -2535,7 +2535,7 @@ < 2265600000 950000 726 >; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>; qcom,bw-tbl = Loading @@ -2560,6 +2560,21 @@ qcom,bytes-per-beat = <16>; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 300000 1144 >, < 422400 2288 >, < 652800 3051 >, < 883200 5996 >, < 1190400 8056 >, < 1497600 10101 >, < 1728000 12145 >, < 2649600 16250 >; }; }; qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", Loading
arch/arm/boot/dts/qcom/fsm9900.dtsi +13 −1 Original line number Diff line number Diff line Loading @@ -663,7 +663,7 @@ "tsens_tz_sensor5", "tsens_tz_sensor6"; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>, <2 512>; qcom,bw-tbl = Loading @@ -674,6 +674,18 @@ < 6103 /* 800 MHz */ >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 300000 572 >, < 422400 1144 >, < 883200 2342 >, < 1190400 3509 >, < 2265600 6103 >; }; }; qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", Loading
arch/arm/boot/dts/qcom/mdm9630.dtsi +11 −1 Original line number Diff line number Diff line Loading @@ -751,7 +751,7 @@ cpu-vdd-supply = <&pmd9635_l3_corner_ao>; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>; qcom,bw-tbl = Loading @@ -760,6 +760,16 @@ < 3051 /* 400 MHz */ >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 600000 1266 >, < 787200 2540 >, < 1152000 3051 >; }; }; qcom,msm-cpufreq@0 { reg = <0 4>; compatible = "qcom,msm-cpufreq"; Loading
arch/arm/boot/dts/qcom/msm8226.dtsi +10 −1 Original line number Diff line number Diff line Loading @@ -1004,7 +1004,7 @@ cpu-vdd-supply = <&apc_vreg_corner>; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>; qcom,bw-tbl = Loading @@ -1014,6 +1014,15 @@ < 4066 /* 533 MHz */ >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 787200 1525 >, < 1785600 4066 >; }; }; qcom,msm-cpufreq@0 { reg = <0 4>; compatible = "qcom,msm-cpufreq"; Loading
arch/arm/boot/dts/qcom/msm8610.dtsi +11 −1 Original line number Diff line number Diff line Loading @@ -514,7 +514,7 @@ cpu-vdd-supply = <&apc_vreg_corner>; }; qcom,cpubw { cpubw: qcom,cpubw { compatible = "qcom,cpubw"; qcom,cpu-mem-ports = <1 512>; qcom,bw-tbl = Loading @@ -523,6 +523,16 @@ < 2540 /* 333 MHz */ >; }; devfreq-cpufreq { cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 384000 762 >, < 787200 1525 >, < 1190400 2540 >; }; }; qcom,msm-cpufreq@0 { reg = <0 4>; compatible = "qcom,msm-cpufreq"; Loading